公开(公告)号：US08024522B1

公开(公告)日：2011-09-20

申请号：US12030851

申请日：2008-02-13

申请人： John Gregory Favor ,  Paul G. Chan ,  Graham Ricketson Murphy ,  Joseph Byron Rowlands

发明人： John Gregory Favor ,  Paul G. Chan ,  Graham Ricketson Murphy ,  Joseph Byron Rowlands

IPC分类号： G06F9/00 ,  G06F13/00

CPC分类号： G06F9/3857 ,  G06F9/3004 ,  G06F9/3808 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3863 ,  G06F12/0875 ,  Y02D10/13

摘要： A processor includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them. At least some of the active memory operations access the memory in an execution order that is different from the program order. During the operation of the circuit, none of the operations of a given trace has any effect on the execution unit's architectural state prior to committing that trace. Each trace becomes eligible for commitment after all operations in the trace complete executing. The circuit also includes a sub-circuit that holds memory operation ordering information corresponding to the active memory operations. The sub-circuit detects violations of ordering constraints. After each trace is committed, the sub-circuit invalidates all of the memory operation ordering information associated with the trace.

摘要翻译： 处理器包括用于跟踪基于跟踪的执行的存储器操作的电路。 每个跟踪包括包括零个或多个存储器操作的一系列操作。 正在执行的存储器操作形成一组在其间具有预定义的程序顺序的活动存储器操作。 至少一些主动存储器操作以与程序顺序不同的执行顺序访问存储器。 在电路运行期间，在提交跟踪之前，给定跟踪的任何操作都不会对执行单元的架构状态产生任何影响。 轨迹中的所有操作完成执行后，每个轨迹都将有资格获得承诺。 该电路还包括保持对应于活动存储器操作的存储器操作排序信息的子电路。 子电路检测到排序限制的违规。 在每个跟踪提交之后，子电路使与跟踪相关联的所有存储器操作排序信息无效。

公开(公告)号：US08010745B1

公开(公告)日：2011-08-30

申请号：US12030859

申请日：2008-02-13

申请人： John Gregory Favor ,  Paul G. Chan ,  Graham Ricketson Murphy ,  Joseph Byron Rowlands

发明人： John Gregory Favor ,  Paul G. Chan ,  Graham Ricketson Murphy ,  Joseph Byron Rowlands

IPC分类号： G06F9/00 ,  G06F13/00

CPC分类号： G06F9/3808 ,  G06F9/3017 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3861

摘要： An embodiment of the present invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. When a memory operation attempts to update a cache line that may not be updated, the circuit attempts to upgrade the cache line. If this fails, a rollback request is generated that indicates the trace involved. The checkpoint locations associated with the indicated trace are overwritten along with those locations associated with all younger traces.

摘要翻译： 本发明的一个实施例包括用于跟踪基于跟踪的执行的存储器操作的电路。 每个跟踪包括包括零个或多个存储器操作的一系列操作。 正在执行的存储器操作形成一组活动存储器操作，它们之间具有预定义的程序顺序和相应的排序限制。 至少一些主动存储器操作以与程序顺序不同的执行顺序访问存储器。 检查点条目与每个跟踪相关联。 当内存操作尝试更新可能未更新的高速缓存行时，该电路会尝试升级缓存行。 如果失败，则会生成一个回滚请求，指示涉及的跟踪。 与指示轨迹相关联的检查点位置与与所有较年轻轨迹相关联的那些位置被覆盖。

公开(公告)号：US07779307B1

公开(公告)日：2010-08-17

申请号：US12030857

申请日：2008-02-13

申请人： John Gregory Favor ,  Paul G. Chan ,  Graham Ricketson Murphy ,  Joseph Byron Rowlands

发明人： John Gregory Favor ,  Paul G. Chan ,  Graham Ricketson Murphy ,  Joseph Byron Rowlands

IPC分类号： G06F11/00

CPC分类号： G06F11/1407

摘要： An embodiment of the present invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. There is a one-to-one correspondence between checkpoint entries and memory operation ordering entries. Each checkpoint entry refers to a checkpoint location. Rollback requests cause the circuit to overwrite checkpoint entries associated with the corresponding trace.

摘要翻译： 本发明的一个实施例包括用于跟踪基于跟踪的执行的存储器操作的电路。 每个跟踪包括包括零个或多个存储器操作的一系列操作。 正在执行的存储器操作形成一组活动存储器操作，它们之间具有预定义的程序顺序和相应的排序限制。 至少一些主动存储器操作以与程序顺序不同的执行顺序访问存储器。 检查点条目与每个跟踪相关联。 检查点条目和内存操作顺序条目之间存在一一对应关系。 每个检查点条目指的是检查点位置。 回滚请求导致电路覆盖与相应跟踪相关联的检查点条目。

公开(公告)号：US08370576B1

公开(公告)日：2013-02-05

申请号：US12030858

申请日：2008-02-13

申请人： John Gregory Favor ,  Paul G. Chan ,  Graham Ricketson Murphy ,  Joseph Byron Rowlands

发明人： John Gregory Favor ,  Paul G. Chan ,  Graham Ricketson Murphy ,  Joseph Byron Rowlands

IPC分类号： G06F12/00

CPC分类号： G06F12/0855 ,  G06F9/3863 ,  Y02D10/13

摘要： An embodiment of the present invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. At least some of the active memory operations access the memory in an execution order that is different from the program order. The circuit includes a first memory that caches data accessed by the memory operations. This memory is partitioned into N banks. Checkpoint entries, which are stored in a second memory also partitioned into N banks, are associated with each trace. Each entry refers to a checkpoint location in the first memory. A sub-circuit receives rollback requests and responds by overwriting checkpoint locations. Each of the N memory units consisting of a bank in the first memory and the corresponding bank in the second memory may be rolled back independently and concurrently with other memory units.

摘要翻译： 本发明的一个实施例包括用于跟踪基于跟踪的执行的存储器操作的电路。 每个跟踪包括包括零个或多个存储器操作的一系列操作。 至少一些主动存储器操作以与程序顺序不同的执行顺序访问存储器。 该电路包括缓存由存储器操作访问的数据的第一存储器。 该内存被划分为N个存储区。 存储在也划分为N个存储区的第二个存储器中的检查点条目与每个跟踪相关联。 每个条目是指第一个内存中的检查点位置。 子电路接收回滚请求并通过覆盖检查点位置进行响应。 由第一存储器中的存储体和第二存储器中的相应存储体组成的N个存储器单元中的每一个可以独立地并与其它存储器单元一起回滚。

公开(公告)号：US08019944B1

公开(公告)日：2011-09-13

申请号：US12030862

申请日：2008-02-13

申请人： John Gregory Favor ,  Paul G. Chan ,  Graham Ricketson Murphy ,  Joseph Byron Rowlands

发明人： John Gregory Favor ,  Paul G. Chan ,  Graham Ricketson Murphy ,  Joseph Byron Rowlands

IPC分类号： G06F9/00 ,  G06F13/00

CPC分类号： G06F9/3808 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/384 ,  G06F9/3857 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/3867 ,  G06F9/3873 ,  G06F12/0831 ,  G06F2212/507 ,  Y02D10/13

摘要： An embodiment of the present invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. Violations of the ordering constraints may be signaled too late to prevent an update of the cached data associated with the memory operations. A sub-circuit detects this condition and invalidates the checkpoint locations indicated by the checkpoint entries associated with the trace experiencing the violation and all younger traces.

摘要翻译： 本发明的一个实施例包括用于跟踪基于跟踪的执行的存储器操作的电路。 每个跟踪包括包括零个或多个存储器操作的一系列操作。 正在执行的存储器操作形成一组活动存储器操作，它们之间具有预定义的程序顺序和相应的排序限制。 至少一些主动存储器操作以与程序顺序不同的执行顺序访问存储器。 检查点条目与每个跟踪相关联。 违反订购约束的信号可能太晚，以防止与存储器操作相关联的缓存数据的更新。 子电路检测到这种情况，并使由与经历违规的跟踪相关联的检查点条目指示的检查点位置和所有较年轻的跟踪无效。

公开(公告)号：US08370609B1

公开(公告)日：2013-02-05

申请号：US12030854

申请日：2008-02-13

申请人： John Gregory Favor ,  Paul G. Chan ,  Graham Ricketson Murphy ,  Joseph Byron Rowlands

发明人： John Gregory Favor ,  Paul G. Chan ,  Graham Ricketson Murphy ,  Joseph Byron Rowlands

IPC分类号： G06F9/312

CPC分类号： G06F9/3808 ,  G06F9/3834 ,  G06F9/3863 ,  G06F11/3636

摘要： This invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. Each entry refers to a checkpoint location. Memory operation ordering entries correspond to each one of the active memory operations. Violations of the ordering constraints result in overwriting the checkpoint locations associated with the selected trace as well as the checkpoint locations associated with traces that are younger than the selected trace.

摘要翻译： 本发明包括用于跟踪基于跟踪的执行的存储器操作的电路。 每个跟踪包括包括零个或多个存储器操作的一系列操作。 正在执行的存储器操作形成一组活动存储器操作，它们之间具有预定义的程序顺序和相应的排序限制。 至少一些主动存储器操作以与程序顺序不同的执行顺序访问存储器。 检查点条目与每个跟踪相关联。 每个条目指的是检查点位置。 存储器操作排序条目对应于每个活动存储器操作。 违反排序限制导致覆盖与所选跟踪相关联的检查点位置以及与所选跟踪较年轻的跟踪关联的检查点位置。

公开(公告)号：US08051247B1

公开(公告)日：2011-11-01

申请号：US12030846

申请日：2008-02-13

申请人： John Gregory Favor ,  Paul G. Chan ,  Graham Ricketson Murphy ,  Joseph Byron Rowlands

发明人： John Gregory Favor ,  Paul G. Chan ,  Graham Ricketson Murphy ,  Joseph Byron Rowlands

IPC分类号： G06F9/00 ,  G06F13/00

CPC分类号： G06F9/3004 ,  G06F9/3808 ,  G06F9/3834 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3863

摘要： A circuit for tracking memory operations with trace-based execution is disclosed. Each trace includes a sequence of operations that includes zero or more of the memory operations. The memory operations being executed form a set of active memory operations that have a predefined program order among them. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. Each entry refers to a checkpoint location. Executing one of the active memory operations updates a checkpoint location. During the operation of the circuit, none of the operations of a given trace has any effect on the execution unit's architectural state prior to committing that trace. Each trace becomes eligible for commitment after all operations in the trace complete executing. After the trace is committed, all of the checkpoint entries associated with the trace are invalidated.

摘要翻译： 公开了一种用于跟踪基于跟踪的执行的存储器操作的电路。 每个跟踪包括包括零个或多个存储器操作的一系列操作。 正在执行的存储器操作形成一组在其间具有预定义的程序顺序的活动存储器操作。 至少一些主动存储器操作以与程序顺序不同的执行顺序访问存储器。 检查点条目与每个跟踪相关联。 每个条目指的是检查点位置。 执行其中一个活动内存操作更新检查点位置。 在电路运行期间，在提交跟踪之前，给定跟踪的任何操作都不会对执行单元的架构状态产生任何影响。 轨迹中的所有操作完成执行后，每个轨迹都将有资格获得承诺。 提交跟踪后，与跟踪相关联的所有检查点条目都将失效。

公开(公告)号：US07877630B1

公开(公告)日：2011-01-25

申请号：US12030852

申请日：2008-02-13

申请人： John Gregory Favor ,  Paul G. Chan ,  Graham Ricketson Murphy ,  Joseph Byron Rowlands

发明人： John Gregory Favor ,  Paul G. Chan ,  Graham Ricketson Murphy ,  Joseph Byron Rowlands

IPC分类号： G06F11/00

CPC分类号： G06F11/3636 ,  G06F9/3004 ,  G06F9/3808 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3863 ,  G06F11/3648

摘要： This invention includes a circuit for tracking memory operations with trace-based execution. Each trace includes a sequence of operations that includes zero or more of the memory operations. Traces execute atomically and become eligible for commitment after all the operations in the trace have executed. The memory operations being executed form a set of active memory operations that have a predefined program order among them and corresponding ordering constraints. At least some of the active memory operations access the memory in an execution order that is different from the program order. Checkpoint entries are associated with each trace. Each entry refers to a checkpoint location. Memory operation ordering entries correspond to each one of the active memory operations. Rollback requests result in overwriting the checkpoint locations associated with the selected trace as well as the checkpoint locations associated with traces that are younger than the selected trace.

摘要翻译： 本发明包括用于跟踪基于跟踪的执行的存储器操作的电路。 每个跟踪包括包括零个或多个存储器操作的一系列操作。 跟踪中的所有操作执行完毕后，跟踪将以原子方式执行并成为合格的承诺。 正在执行的存储器操作形成一组活动存储器操作，它们之间具有预定义的程序顺序和相应的排序限制。 至少一些主动存储器操作以与程序顺序不同的执行顺序访问存储器。 检查点条目与每个跟踪相关联。 每个条目指的是检查点位置。 存储器操作排序条目对应于每个活动存储器操作。 回滚请求导致覆盖与所选跟踪相关联的检查点位置以及与所选跟踪较年轻的跟踪关联的检查点位置。

公开(公告)号：US08732430B2

公开(公告)日：2014-05-20

申请号：US13069337

申请日：2011-03-22

申请人： Zoran Radovic ,  Graham Ricketson Murphy ,  Paul J. Jordan ,  John G. Johnson

发明人： Zoran Radovic ,  Graham Ricketson Murphy ,  Paul J. Jordan ,  John G. Johnson

IPC分类号： G06F12/10 ,  G06F12/02

CPC分类号： G06F12/10 ,  G06F8/315 ,  G06F12/02 ,  G06F12/0253

摘要： The disclosed embodiments provide a system that uses unused bits in a memory pointer. During operation, the system determines a set of address bits in a address space that will not be needed for addressing purposes during program operation. Subsequently, the system stores data associated with the memory pointer in this set of address bits. The system masks this set of address bits when using the memory pointer to access the memory address associated with the memory pointer. Storing additional data in unused pointer bits can reduce the number of memory accesses for a program and improve program performance and/or reliability.

摘要翻译： 所公开的实施例提供了使用存储器指针中的未使用位的系统。 在操作期间，系统确定地址空间中的一组地址位，在编程操作期间不需要寻址目的。 随后，系统将与存储器指针相关联的数据存储在该组地址位中。 当使用存储器指针访问与存储器指针相关联的存储器地址时，系统将对该组地址位进行掩蔽。 将附加数据存储在未使用的指针位中可以减少程序的存储器访问次数，并提高程序性能和/或可靠性。

公开(公告)号：US08756363B2

公开(公告)日：2014-06-17

申请号：US13178240

申请日：2011-07-07

申请人： Zoran Radovic ,  Graham Ricketson Murphy ,  Bharat K. Daga

发明人： Zoran Radovic ,  Graham Ricketson Murphy ,  Bharat K. Daga

IPC分类号： G06F12/00

CPC分类号： G06F21/52 ,  G06F11/073 ,  G06F11/0763 ,  G06F11/1666

摘要： Systems and methods for efficient memory corruption detection in a processor. A processor detects a first data structure is to be allocated in a physical memory. The physical memory may be a DRAM with a spare bank of memory reserved for a hardware failover mechanism. Either the processor or an operating system (OS) determines a first version number corresponding to the first data structure. During initialization of the first data structure, the first version number may be stored in a first location in the spare bank. The processor receives from the OS a pointer holding the first version number. When the processor executes memory access operations targeting the first data structure, the processor compares the first version number with a third version number stored in a location in the physical memory indicated by the memory access address. The processor may set a trap in response to determining a mismatch.

摘要翻译： 处理器中有效的内存损坏检测的系统和方法。 处理器检测将在物理存储器中分配第一数据结构。 物理存储器可以是具有为硬件故障切换机制保留的备用存储体的DRAM。 处理器或操作系统（OS）都确定与第一数据结构对应的第一版本号。 在第一数据结构的初始化期间，第一版本号可以存储在备用存储体中的第一位置。 处理器从OS接收保持第一版本号的指针。 当处理器执行针对第一数据结构的存储器访问操作时，处理器将第一版本号与存储在由存储器访问地址指示的物理存储器中的位置中的第三版本号进行比较。 响应于确定不匹配，处理器可以设置陷阱。