Interchangeable preconcentrator connector assembly
    5.
    发明授权
    Interchangeable preconcentrator connector assembly 有权
    可互换的预浓缩器连接器组件

    公开(公告)号:US08178045B2

    公开(公告)日:2012-05-15

    申请号:US12337449

    申请日:2008-12-17

    IPC分类号: G01N30/00 G01N30/08

    摘要: An interchangeable preconcentrator assembly comprises an outer housing and an inner housing defining a chamber. A biased urging member is held at least partially within the outer housing and slidably biased toward a surface of the inner housing. When the biased urging member is at least partially retracted, a space is defined between the urging member and the surface of the inner housing for accommodating at least one preconcentrator chip. A continuous fluid flow path is defined through the outer housing and through the space. The interchangeable preconcentrator assembly may further comprise at least one modular preconcentrator carriage.

    摘要翻译: 可互换的预浓缩器组件包括外壳体和限定腔室的内壳体。 偏压推动构件至少部分地保持在外壳体内并且可滑动地偏压到内壳体的表面。 当偏压推动构件至少部分地缩回时,在推动构件和内壳体的表面之间限定一个空间,用于容纳至少一个预浓缩器芯片。 连续的流体流动路径通过外部壳体并通过该空间来限定。 可互换的预浓缩器组件还可以包括至少一个模块化预浓缩器托架。

    Interchangeable preconcentrator connector assembly
    7.
    发明申请
    Interchangeable preconcentrator connector assembly 有权
    可互换的预浓缩器连接器组件

    公开(公告)号:US20090249958A1

    公开(公告)日:2009-10-08

    申请号:US12337449

    申请日:2008-12-17

    IPC分类号: B01D50/00

    摘要: An interchangeable preconcentrator assembly comprises an outer housing and an inner housing defining a chamber. A biased urging member is held at least partially within the outer housing and slidably biased toward a surface of the inner housing. When the biased urging member is at least partially retracted, a space is defined between the urging member and the surface of the inner housing for accommodating at least one preconcentrator chip. A continuous fluid flow path is defined through the outer housing and through the space. The interchangeable preconcentrator assembly may further comprise at least one modular preconcentrator carriage.

    摘要翻译: 可互换的预浓缩器组件包括外壳体和限定腔室的内壳体。 偏压推动构件至少部分地保持在外壳体内并且可滑动地偏压到内壳体的表面。 当偏压推动构件至少部分地缩回时,在推动构件和内壳体的表面之间限定一个空间,用于容纳至少一个预浓缩器芯片。 连续的流体流动路径通过外部壳体并通过该空间来限定。 可互换的预浓缩器组件还可以包括至少一个模块化预浓缩器托架。

    Frequency counter based analog-to-digital converter
    8.
    发明授权
    Frequency counter based analog-to-digital converter 有权
    基于频率计的模数转换器

    公开(公告)号:US07948421B2

    公开(公告)日:2011-05-24

    申请号:US12477033

    申请日:2009-06-02

    IPC分类号: H03M1/12

    CPC分类号: H03M1/60 G04F10/005

    摘要: An analog-to-digital converter (ADC) is provided. The ADC includes a variable oscillator, a frequency divider, a clock circuit, and a counter. The variable oscillator is coupled to a sensor and configured to generate an oscillating signal based on a measurement generated by the sensor. The frequency divider is coupled to the variable oscillator and configured to divide a frequency of the oscillating signal. The clock circuit is configured to generate a clock signal at a defined frequency. The counter is coupled to the frequency divider and to the clock and is configured to generate a bit stream representative of a first number of periods of the clock signal during a second number of periods of the divided oscillating signal.

    摘要翻译: 提供了一个模拟 - 数字转换器(ADC)。 ADC包括可变振荡器,分频器,时钟电路和计数器。 可变振荡器耦合到传感器并且被配置为基于由传感器产生的测量来产生振荡信号。 分频器耦合到可变振荡器并且被配置为分频振荡信号的频率。 时钟电路被配置为以定义的频率产生时钟信号。 计数器耦合到分频器和时钟,并被配置为在分频振荡信号的第二数量周期期间产生表示时钟信号的第一数量周期的比特流。

    FREQUENCY COUNTER BASED ANALOG-TO-DIGITAL CONVERTER
    9.
    发明申请
    FREQUENCY COUNTER BASED ANALOG-TO-DIGITAL CONVERTER 有权
    基于频率计数器的模拟数字转换器

    公开(公告)号:US20090315749A1

    公开(公告)日:2009-12-24

    申请号:US12477033

    申请日:2009-06-02

    IPC分类号: H03M1/12

    CPC分类号: H03M1/60 G04F10/005

    摘要: An analog-to-digital converter (ADC) is provided. The ADC includes a variable oscillator, a frequency divider, a clock circuit, and a counter. The variable oscillator is coupled to a sensor and configured to generate an oscillating signal based on a measurement generated by the sensor. The frequency divider is coupled to the variable oscillator and configured to divide a frequency of the oscillating signal. The clock circuit is configured to generate a clock signal at a defined frequency. The counter is coupled to the frequency divider and to the clock and is configured to generate a bit stream representative of a first number of periods of the clock signal during a second number of periods of the divided oscillating signal.

    摘要翻译: 提供了一个模拟 - 数字转换器(ADC)。 ADC包括可变振荡器,分频器,时钟电路和计数器。 可变振荡器耦合到传感器并且被配置为基于由传感器产生的测量来产生振荡信号。 分频器耦合到可变振荡器并且被配置为分频振荡信号的频率。 时钟电路被配置为以定义的频率产生时钟信号。 计数器耦合到分频器和时钟,并被配置为在分频振荡信号的第二数量周期期间产生表示时钟信号的第一数量周期的比特流。