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公开(公告)号：US20090265675A1
公开(公告)日：2009-10-22
申请号：US12103825
申请日：2008-04-16
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , H01L27/088 , H01L29/4238 , H01L29/78
摘要： A method for reducing variation in a desired property between transistors in an integrated circuit that is fabricated with a given process. The process is characterized to form a mathematical model that associates changes in polysilicon density and active density in the integrate circuit with changes in gate length and gate width in the transistors, and associates changes in the gate length and the gate width to the desired property. The integrated circuit is laid out with space sufficient to adjust the gate length and the gate width of the transistors without violating design rules of the transistors. The integrated circuit is divided into portions, and for at least a given one of the portions of the integrated circuit, the polysilicon density and the active density of the given portion is measured. For at least one of the transistors in the given portion of the integrated circuit, at least one of the gate length and the gate width of the transistor is selectively adjusted according to the mathematical model, based on at least one of the polysilicon density and the active density of the given portion, to reduce variation in the desired property between the transistors in the integrated circuit.
摘要翻译： 一种用于减少用给定工艺制造的集成电路中的晶体管之间期望特性的变化的方法。 该过程的特征在于形成数学模型，其将积分电路中的多晶硅密度和有源密度的变化与晶体管中的栅极长度和栅极宽度的变化相关联，并且将栅极长度和栅极宽度的变化关联到期望的性质。 集成电路布置有足以调节晶体管的栅极长度和栅极宽度的空间，而不违反晶体管的设计规则。 集成电路被分成多个部分，并且对于集成电路的至少一个给定的部分，测量给定部分的多晶硅密度和有效密度。 对于集成电路的给定部分中的至少一个晶体管，根据数学模型，基于多晶硅密度和晶体管的至少一个来选择性地调节晶体管的栅极长度和栅极宽度中的至少一个 给定部分的有效密度，以减少集成电路中的晶体管之间的期望特性的变化。
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公开(公告)号：US07895550B2
公开(公告)日：2011-02-22
申请号：US12103825
申请日：2008-04-16
IPC分类号： G06F17/50
CPC分类号： H01L27/0207 , H01L27/088 , H01L29/4238 , H01L29/78
摘要： A method for reducing variation in a desired property between transistors in an integrated circuit that is fabricated with a given process. The process is characterized to form a mathematical model that associates changes in polysilicon density and active density in the integrate circuit with changes in gate length and gate width in the transistors, and associates changes in the gate length and the gate width to the desired property. The integrated circuit is laid out with space sufficient to adjust the gate length and the gate width of the transistors without violating design rules of the transistors. The integrated circuit is divided into portions, and for at least a given one of the portions of the integrated circuit, the polysilicon density and the active density of the given portion is measured. For at least one of the transistors in the given portion of the integrated circuit, at least one of the gate length and the gate width of the transistor is selectively adjusted according to the mathematical model, based on at least one of the polysilicon density and the active density of the given portion, to reduce variation in the desired property between the transistors in the integrated circuit.
摘要翻译： 一种用于减少用给定工艺制造的集成电路中的晶体管之间期望特性的变化的方法。 该过程的特征在于形成数学模型，其将积分电路中的多晶硅密度和有源密度的变化与晶体管中的栅极长度和栅极宽度的变化相关联，并且将栅极长度和栅极宽度的变化关联到期望的性质。 集成电路布置有足以调节晶体管的栅极长度和栅极宽度的空间，而不违反晶体管的设计规则。 集成电路被分成多个部分，并且对于集成电路的至少一个给定的部分，测量给定部分的多晶硅密度和有效密度。 对于集成电路的给定部分中的至少一个晶体管，根据数学模型，基于多晶硅密度和晶体管的至少一个来选择性地调节晶体管的栅极长度和栅极宽度中的至少一个 给定部分的有效密度，以减少集成电路中的晶体管之间的期望特性的变化。
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公开(公告)号：US08384226B2
公开(公告)日：2013-02-26
申请号：US12885722
申请日：2010-09-20
IPC分类号： H01L23/48 , H01L27/108 , H01L21/00
CPC分类号： H01G4/228 , H01G4/30 , H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A device fabricated on a chip is disclosed. The device generally includes (A) a first pattern and a second pattern both created in an intermediate conductive layer of the chip, (B) at least one via created in an insulating layer above the intermediate conductive layer and (C) a first bump created in a top conductive layer above the insulating layer. The first pattern generally establishes a first of a plurality of plates of a first capacitor. The via may be aligned with the second pattern. The first bump may (i) be located directly above the first plate, (ii) establish a second of the plates of the first capacitor, (iii) be suitable for flip-chip bonding, (iv) connect to the second pattern through the via such that both of the plates of the first capacitor are accessible in the intermediate conductive layer. The first pattern and the second pattern may be shaped as interlocking combs.
摘要翻译： 公开了一种在芯片上制造的器件。 该装置通常包括（A）在芯片的中间导电层中产生的第一图案和第二图案，（B）在中间导电层上方的绝缘层中形成的至少一个通孔，（C）产生的第一凸起 在绝缘层上方的顶部导电层中。 第一图案通常建立第一电容器的多个板中的第一个。 通孔可以与第二图案对准。 第一凸块可以（i）位于第一板的正上方，（ii）建立第一电容器的第二板，（iii）适于倒装芯片接合，（iv）通过 通过使得第一电容器的两个板可在中间导电层中接近。 第一图案和第二图案可以被成形为互锁梳。
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公开(公告)号：US20110006395A1
公开(公告)日：2011-01-13
申请号：US12885722
申请日：2010-09-20
CPC分类号： H01G4/228 , H01G4/30 , H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A device fabricated on a chip is disclosed. The device generally includes (A) a first pattern and a second pattern both created in an intermediate conductive layer of the chip, (B) at least one via created in an insulating layer above the intermediate conductive layer and (C) a first bump created in a top conductive layer above the insulating layer. The first pattern generally establishes a first of a plurality of plates of a first capacitor. The via may be aligned with the second pattern. The first bump may (i) be located directly above the first plate, (ii) establish a second of the plates of the first capacitor, (iii) be suitable for flip-chip bonding, (iv) connect to the second pattern through the via such that both of the plates of the first capacitor are accessible in the intermediate conductive layer. The first pattern and the second pattern may be shaped as interlocking combs.
摘要翻译： 公开了一种在芯片上制造的器件。 该装置通常包括（A）在芯片的中间导电层中产生的第一图案和第二图案，（B）在中间导电层上方的绝缘层中形成的至少一个通孔，（C）产生的第一凸起 在绝缘层上方的顶部导电层中。 第一图案通常建立第一电容器的多个板中的第一个。 通孔可以与第二图案对准。 第一凸块可以（i）位于第一板的正上方，（ii）建立第一电容器的第二板，（iii）适于倒装芯片接合，（iv）通过 通过使得第一电容器的两个板可在中间导电层中接近。 第一图案和第二图案可以被成形为互锁梳。
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公开(公告)号：US20080018419A1
公开(公告)日：2008-01-24
申请号：US11741195
申请日：2007-04-27
CPC分类号： H01G4/228 , H01G4/30 , H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A device fabricated on a chip is disclosed. The device generally includes (A) a first pattern and a second pattern both created in an intermediate conductive layer of the chip, (B) at least one via created in an insulating layer above the intermediate conductive layer and (C) a first bump created in a top conductive layer above the insulating layer. The first pattern generally establishes a first of a plurality of plates of a first capacitor. The via may be aligned with the second pattern. The first bump may (i) be located directly above the first plate, (ii) establish a second of the plates of the first capacitor, (iii) be suitable for flip-chip bonding and (iv) connect to the second pattern through the via such that both of the plates of the first capacitor are accessible in the intermediate conductive layer.
摘要翻译： 公开了一种在芯片上制造的器件。 器件通常包括（A）在芯片的中间导电层中产生的第一图案和第二图案，（B）在中间导电层上方的绝缘层中形成的至少一个通孔，（C）产生的第一凸起 在绝缘层上方的顶部导电层中。 第一图案通常建立第一电容器的多个板中的第一个。 通孔可以与第二图案对准。 第一凸块可以（i）位于第一板的正上方，（ii）建立第一电容器的第二板，（iii）适于倒装芯片接合，以及（iv）通过 通过使得第一电容器的两个板可在中间导电层中接近。
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公开(公告)号：US07825522B2
公开(公告)日：2010-11-02
申请号：US11741195
申请日：2007-04-27
IPC分类号： H01L23/48 , H01L27/108
CPC分类号： H01G4/228 , H01G4/30 , H01L23/5223 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： A device fabricated on a chip is disclosed. The device generally includes (A) a first pattern and a second pattern both created in an intermediate conductive layer of the chip, (B) at least one via created in an insulating layer above the intermediate conductive layer and (C) a first bump created in a top conductive layer above the insulating layer. The first pattern generally establishes a first of a plurality of plates of a first capacitor. The via may be aligned with the second pattern. The first bump may (i) be located directly above the first plate, (ii) establish a second of the plates of the first capacitor, (iii) be suitable for flip-chip bonding and (iv) connect to the second pattern through the via such that both of the plates of the first capacitor are accessible in the intermediate conductive layer.
摘要翻译： 公开了一种在芯片上制造的器件。 该装置通常包括（A）在芯片的中间导电层中产生的第一图案和第二图案，（B）在中间导电层上方的绝缘层中形成的至少一个通孔，（C）产生的第一凸起 在绝缘层上方的顶部导电层中。 第一图案通常建立第一电容器的多个板中的第一个。 通孔可以与第二图案对准。 第一凸块可以（i）位于第一板的正上方，（ii）建立第一电容器的第二板，（iii）适于倒装芯片接合，以及（iv）通过 通过使得第一电容器的两个板可在中间导电层中接近。
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