公开(公告)号：US20090265675A1

公开(公告)日：2009-10-22

申请号：US12103825

申请日：2008-04-16

申请人： John Q. Walker ,  Jeffrey P. Burleson ,  Scott A. Service ,  Steven L. Howard

发明人： John Q. Walker ,  Jeffrey P. Burleson ,  Scott A. Service ,  Steven L. Howard

IPC分类号： G06F17/50

CPC分类号： H01L27/0207 ,  H01L27/088 ,  H01L29/4238 ,  H01L29/78

摘要： A method for reducing variation in a desired property between transistors in an integrated circuit that is fabricated with a given process. The process is characterized to form a mathematical model that associates changes in polysilicon density and active density in the integrate circuit with changes in gate length and gate width in the transistors, and associates changes in the gate length and the gate width to the desired property. The integrated circuit is laid out with space sufficient to adjust the gate length and the gate width of the transistors without violating design rules of the transistors. The integrated circuit is divided into portions, and for at least a given one of the portions of the integrated circuit, the polysilicon density and the active density of the given portion is measured. For at least one of the transistors in the given portion of the integrated circuit, at least one of the gate length and the gate width of the transistor is selectively adjusted according to the mathematical model, based on at least one of the polysilicon density and the active density of the given portion, to reduce variation in the desired property between the transistors in the integrated circuit.

摘要翻译： 一种用于减少用给定工艺制造的集成电路中的晶体管之间期望特性的变化的方法。 该过程的特征在于形成数学模型，其将积分电路中的多晶硅密度和有源密度的变化与晶体管中的栅极长度和栅极宽度的变化相关联，并且将栅极长度和栅极宽度的变化关联到期望的性质。 集成电路布置有足以调节晶体管的栅极长度和栅极宽度的空间，而不违反晶体管的设计规则。 集成电路被分成多个部分，并且对于集成电路的至少一个给定的部分，测量给定部分的多晶硅密度和有效密度。 对于集成电路的给定部分中的至少一个晶体管，根据数学模型，基于多晶硅密度和晶体管的至少一个来选择性地调节晶体管的栅极长度和栅极宽度中的至少一个 给定部分的有效密度，以减少集成电路中的晶体管之间的期望特性的变化。

公开(公告)号：US07895550B2

公开(公告)日：2011-02-22

申请号：US12103825

申请日：2008-04-16

申请人： John Q. Walker ,  Jeffrey P. Burleson ,  Scott A. Service ,  Steven L. Howard

发明人： John Q. Walker ,  Jeffrey P. Burleson ,  Scott A. Service ,  Steven L. Howard

IPC分类号： G06F17/50

CPC分类号： H01L27/0207 ,  H01L27/088 ,  H01L29/4238 ,  H01L29/78

摘要： A method for reducing variation in a desired property between transistors in an integrated circuit that is fabricated with a given process. The process is characterized to form a mathematical model that associates changes in polysilicon density and active density in the integrate circuit with changes in gate length and gate width in the transistors, and associates changes in the gate length and the gate width to the desired property. The integrated circuit is laid out with space sufficient to adjust the gate length and the gate width of the transistors without violating design rules of the transistors. The integrated circuit is divided into portions, and for at least a given one of the portions of the integrated circuit, the polysilicon density and the active density of the given portion is measured. For at least one of the transistors in the given portion of the integrated circuit, at least one of the gate length and the gate width of the transistor is selectively adjusted according to the mathematical model, based on at least one of the polysilicon density and the active density of the given portion, to reduce variation in the desired property between the transistors in the integrated circuit.

摘要翻译： 一种用于减少用给定工艺制造的集成电路中的晶体管之间期望特性的变化的方法。 该过程的特征在于形成数学模型，其将积分电路中的多晶硅密度和有源密度的变化与晶体管中的栅极长度和栅极宽度的变化相关联，并且将栅极长度和栅极宽度的变化关联到期望的性质。 集成电路布置有足以调节晶体管的栅极长度和栅极宽度的空间，而不违反晶体管的设计规则。 集成电路被分成多个部分，并且对于集成电路的至少一个给定的部分，测量给定部分的多晶硅密度和有效密度。 对于集成电路的给定部分中的至少一个晶体管，根据数学模型，基于多晶硅密度和晶体管的至少一个来选择性地调节晶体管的栅极长度和栅极宽度中的至少一个 给定部分的有效密度，以减少集成电路中的晶体管之间的期望特性的变化。

公开(公告)号：US20100244276A1

公开(公告)日：2010-09-30

申请号：US12725169

申请日：2010-03-16

申请人： Jeffrey P. Burleson ,  Shahriar Moinian ,  John Osenbach ,  Jayanthi Pallinti

发明人： Jeffrey P. Burleson ,  Shahriar Moinian ,  John Osenbach ,  Jayanthi Pallinti

IPC分类号： H01L23/50 ,  H01L21/60

CPC分类号： H01L25/18 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L24/92 ,  H01L25/0657 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16235 ,  H01L2224/1703 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/81203 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06572 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15311 ,  H01L2924/15321 ,  H01L2924/157 ,  H01L2924/00012 ,  H01L2924/00

摘要： An electronics package 100 comprising a substrate 105 having a planar surface 107, a memory die 110 and a logic die 120. Memory circuit components 112 interconnected to memory die contacts 114 located on an outer surface 116 of a face 118 of the memory die. Logic circuit components 122 interconnected to logic die contacts 124 located on an outer surface 126 of a face 128 of the logic die. Memory die contacts and the logic die contacts are interconnected such that the face of the memory die opposes the face of the logic die. A plurality of bonds 130 interconnect input-output contacts 132 on the planar surface of the substrate, to external die contacts 135 on one of the face of the logic die or the face of the memory die. One face opposes the planar surface, the other face is not directly connected to the interconnect input-output contacts.

摘要翻译： 包括具有平坦表面107，存储管芯110和逻辑管芯120的衬底105的电子封装100.存储器电路部件112互连到位于存储器管芯的表面118的外表面116上的存储器管芯触点114。 逻辑电路部件122互连到位于逻辑管芯的表面128的外表面126上的逻辑管接头124。 存储器管芯触点和逻辑管芯触头互连，使得存储器管芯的表面与逻辑管芯的表面相对。 多个键130将衬底的平坦表面上的输入 - 输出触点132互连到逻辑管芯的一个面上的存储器管芯的外部管芯触点135。 一个面对着平面，另一个面不直接连接到互连输入 - 输出触点。