-
1.发明授权Self aligning in-situ ellipsometer and method of using for process monitoring 失效自适应原位椭偏仪及其用于过程监控的方法
公开(公告)号：US5408322A
公开(公告)日：1995-04-18
申请号：US52888
申请日：1993-04-26
申请人： Jon S. Hsu , Bhola N. De , Rodney L. Robison , Tugrul Yasar
发明人： Jon S. Hsu , Bhola N. De , Rodney L. Robison , Tugrul Yasar
CPC分类号： G01N21/211 , G01B11/065
摘要： An ellipsometric measuring system is set-up in association with a vacuum chamber on a production line for thin film samples. The ellipsometer has a scanner for directing the incident light beam to different locations on a thin film sample, and the ellipsometer also has an aperture for limiting the reflected light beam received by the photodetector. The scanner implements a method of aligning the incident beam to a selected surface of the sample. The scanner and the aperture are used to provide a finer adjustment of the incident beam with respect to the selected surface. The ellipsometric measuring system further uses test thin film samples with known film thicknesses and index or refractions to calculate a value for the angle of incidence of the incident light beam.
摘要翻译： 椭圆测量系统与薄膜样品生产线上的真空室相关联地设置。 椭偏仪具有用于将入射光束引导到薄膜样品上的不同位置的扫描仪，并且椭偏仪还具有用于限制由光电检测器接收的反射光束的孔。 扫描器实现将入射光束与样品的选定表面对准的方法。 扫描器和孔径用于提供相对于所选择的表面的入射光束的更精细的调整。 椭圆测量系统还使用具有已知膜厚度和折射率或折射率的测试薄膜样品来计算入射光束入射角的值。
-
公开(公告)号：US07901545B2
公开(公告)日：2011-03-08
申请号：US10811326
申请日：2004-03-26
IPC分类号： C23C14/34
CPC分类号： H01L21/2855 , C23C14/025 , C23C14/046 , C23C14/345 , C23C14/3492 , H01J37/32706 , H01J2237/3327 , H01L21/76843 , H01L21/76865 , H01L21/76873 , H01L2221/1078 , H01L2221/1089
摘要： An iPVD system is programmed to deposit uniform material, such as barrier material, into high aspect ratio nano-size features on semiconductor substrates using a process which enhances the sidewall coverage compared to the field and bottom coverage(s) while minimizing or eliminating overhang within a vacuum chamber. The iPVD system is operated at low target power and high pressure >50 mT to sputter material from the target. RF energy is coupled into the chamber to form a high density plasma. A small RF bias (less than a few volts) can be applied to aid in enhancing the coverage, especially at the bottom.
-
3.发明授权Electrical contacts for integrated circuits and methods of forming using gas cluster ion beam processing 有权用于集成电路的电触点和使用气体簇离子束处理的成型方法公开(公告)号：US07772110B2
公开(公告)日：2010-08-10
申请号：US11864334
申请日：2007-09-28
IPC分类号： H01L21/4763
CPC分类号： H01L21/76859 , H01J2237/0812 , H01L21/76844 , H01L21/76846 , H01L21/76867 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention describe electrical contacts for integrated circuits and methods of forming using gas cluster ion beam (GCIB) processing. The electrical contacts contain a fused metal-containing layer formed by exposing a patterned structure to a gas cluster ion beam containing a transition metal precursor or a rare earth metal precursor.
摘要翻译： 本发明的实施例描述了用于集成电路的电触点和使用气体簇离子束（GCIB）处理的形成方法。 电触点包含通过将图案化结构暴露于含有过渡金属前体或稀土金属前体的气体簇离子束而形成的熔融金属含有层。
-
4.发明申请METHOD OF DEPOSITING METAL-CONTAINING FILMS BY INDUCTIVELY COUPLED PHYSICAL VAPOR DEPOSITION 审中-公开通过电感耦合物理蒸发沉积沉积含金属膜的方法公开(公告)号：US20090242385A1
公开(公告)日：2009-10-01
申请号：US12058607
申请日：2008-03-28
IPC分类号： C23C14/34
CPC分类号： C23C14/0641 , C23C14/358 , H01J37/321 , H01J37/3426
摘要： A method for depositing a metal-containing film on a substrate using an inductively coupled (ICP) physical vapor deposition (PVD) system. The ICP PVD deposition is performed under process conditions that thermalize neutral sputtered metal atoms by collisions with a process gas and minimize or eliminate exposure of ions to the substrate.
摘要翻译： 一种使用电感耦合（ICP）物理气相沉积（PVD）系统在基片上沉积含金属膜的方法。 ICP PVD沉积在通过与工艺气体碰撞来热化中性溅射金属原子的工艺条件下进行，并最小化或消除离子暴露于衬底。
-
公开(公告)号：US20080087638A1
公开(公告)日：2008-04-17
申请号：US11536758
申请日：2006-09-29
申请人： Jozef Brcka , Rodney L. Robison , Takashi Horiuchi
发明人： Jozef Brcka , Rodney L. Robison , Takashi Horiuchi
CPC分类号： H01J37/3299 , H01J37/32935
摘要： Calibration wafers and methods for calibrating a plasma process performed in a plasma processing apparatus, such as an ionized physical vapor deposition apparatus. The calibration wafer includes one or more selective-redeposition sources that may be used for calibrating a plasma process. The selective-redeposition sources are constructed to promote the redeposition of a controllable and/or measurable amount of material during the plasma process.
摘要翻译： 用于校准在诸如电离物理气相沉积装置的等离子体处理装置中进行的等离子体处理的校准晶片和方法。 校准晶片包括可用于校准等离子体工艺的一个或多个选择性再沉积源。 构建选择性再沉积源以在等离子体工艺期间促进可控和/或可测量的材料的再沉积。
-
公开(公告)号：US08194384B2
公开(公告)日：2012-06-05
申请号：US12178327
申请日：2008-07-23
IPC分类号： H01L21/683 , H01T23/00
CPC分类号： H02N13/00
摘要： An electrostatic chuck configured for high temperature reduced-pressure processing is described. The electrostatic chuck comprises a chuck body having an electrostatic clamp electrode and an optional heating element, and a heat sink body having a heat transfer surface spaced in close relationship with an inner surface of the chuck body, wherein the heat sink body is configured to remove heat from the chuck body due to the close proximity of the inner surface and the heat transfer surface. The electrostatic chuck further comprises a table assembly configured to support the chuck body and the heat sink body, and an expansion joint disposed between the chuck body and the table assembly, and configured to sealably join the chuck body to the table assembly while accommodating for differential thermal expansion of the chuck body and the table assembly.
摘要翻译： 描述了构造用于高温减压处理的静电卡盘。 静电卡盘包括具有静电夹持电极和任选的加热元件的卡盘体，以及具有与卡盘主体的内表面间隔开的传热表面的散热体，其中，散热体被构造成去除 由于内表面和传热表面的紧密接触，来自卡盘体的热量。 所述静电吸盘还包括配置成支撑所述卡盘主体和所述散热体主体的工作台组件，以及设置在所述卡盘主体和所述工作台组件之间的伸缩接头，并且构造成将所述卡盘主体可密封地连接到所述工作台组件，同时容纳差速器 卡盘主体和工作台组件的热膨胀。
-
公开(公告)号：US07776748B2
公开(公告)日：2010-08-17
申请号：US11536902
申请日：2006-09-29
申请人： Jozef Brcka , Rodney L. Robison , Takashi Horiuchi
发明人： Jozef Brcka , Rodney L. Robison , Takashi Horiuchi
IPC分类号： H01L21/302
CPC分类号： H01J37/3299 , H01J37/32935 , H01L22/12 , H01L22/20
摘要： Calibration wafers and methods for calibrating a plasma process performed in a plasma processing apparatus, such as an ionized physical vapor deposition apparatus. The calibration wafer includes one or more selective-redeposition structures for calibrating a plasma process. The selective-redeposition structures receive a controllable and/or measurable amount of redeposited material during the plasma process.
摘要翻译： 用于校准在诸如电离物理气相沉积装置的等离子体处理装置中进行的等离子体处理的校准晶片和方法。 校准晶片包括用于校准等离子体工艺的一个或多个选择性再沉积结构。 选择性再沉积结构在等离子体工艺期间接收可控和/或可测量的再沉积材料。
-
公开(公告)号：US20090242383A1
公开(公告)日：2009-10-01
申请号：US12059649
申请日：2008-03-31
IPC分类号： C23C14/34
CPC分类号： C23C14/50 , H01J37/32623 , H01J37/34 , H01J37/3441
摘要： An IPVD source assembly and method is provided for supplying and ionizing material for coating a semiconductor wafer. The assembly includes a process space containing a plasma and an electrostatic chuck moveable in to and out of the process space. The chuck is configured to support the semiconductor wafer. The assembly further includes a first shield in electrical communication with a table and a second shield. The first shield is configured to shield at least a portion of the electrostatic chuck when the chuck is in the process space and the second shield is configured to shield at least a portion of a space below the electrostatic chuck and the process space. A conducting element electrically connects the second shield to the table to substantially prevent a formation of a second plasma in the space below the electrostatic chuck and the process space.
摘要翻译： 提供IPVD源组件和方法用于供给和电离用于涂覆半导体晶片的材料。 该组件包括含有等离子体的处理空间和可移入和移出工艺空间的静电吸盘。 卡盘构造成支撑半导体晶片。 组件还包括与桌子和第二屏蔽件电连通的第一屏蔽件。 第一屏蔽被配置为当卡盘在处理空间中时屏蔽静电卡盘的至少一部分，并且第二屏蔽构造成屏蔽静电卡盘和处理空间下方的空间的至少一部分。 导电元件将第二屏蔽件电连接到工作台，以基本上防止在静电卡盘和处理空间下方的空间中形成第二等离子体。
-
公开(公告)号：US20090321247A1
公开(公告)日：2009-12-31
申请号：US12555068
申请日：2009-09-08
IPC分类号： C23C14/34
CPC分类号： C23C14/025 , C23C14/046 , C23C14/345 , C23C14/3492 , H01J37/32706 , H01J2237/3327 , H01L21/2855 , H01L21/76843 , H01L21/76865
摘要： A method is provided of operating a deposition system to deposit coating material into high aspect ratio nano-sized features on a patterned substrate that enhances sidewall coverage compared to field area and bottom surface coverage while minimizing or eliminating overhang. The method includes performing a process step with a gross field area deposition rate of about 25 to 70 nm/min and simultaneously etching the barrier layer to establish a net field area deposition rate of about 5 to 40 nm/min. The method may also include first performing a protective layer deposition step with a field area deposition rate of about 5 to 20 nm/min without etching the underlying surface then performing a surface modification step with gross deposition and simultaneous etching at a field modification net deposition rate of about −10 to +40 nm/min.
摘要翻译： 提供了一种操作沉积系统以将涂层材料沉积在图案化衬底上的高纵横比纳米尺寸特征的方法，其增强了与场面积和底面覆盖率相比较，同时最小化或消除悬垂的侧壁覆盖。 该方法包括执行总场积淀积速率为约25至70nm / min的工艺步骤，同时蚀刻阻挡层以建立约5至40nm / min的净场致积率。 该方法还可以包括首先执行具有大约5至20nm / min的场区沉积速率的保护层沉积步骤，而不蚀刻下面的表面，然后在场修正网沉积速率下进行总沉积和同时蚀刻的表面改性步骤 约-10至+ 40nm / min。
-
10.发明申请ELECTRICAL CONTACTS FOR INTEGRATED CIRCUITS AND METHODS OF FORMING USING GAS CLUSTER ION BEAM PROCESSING 有权集成电路的电气接触和使用气体串联离子束加工的成型方法公开(公告)号：US20090085211A1
公开(公告)日：2009-04-02
申请号：US11864334
申请日：2007-09-28
IPC分类号： H01L23/52 , H01L21/425
CPC分类号： H01L21/76859 , H01J2237/0812 , H01L21/76844 , H01L21/76846 , H01L21/76867 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of the invention describe electrical contacts for integrated circuits and methods of forming using gas cluster ion beam (GCIB) processing. The electrical contacts contain a fused metal-containing layer formed by exposing a patterned structure to a gas cluster ion beam containing a transition metal precursor or a rare earth metal precursor.
摘要翻译： 本发明的实施例描述了用于集成电路的电触点和使用气体簇离子束（GCIB）处理的形成方法。 电触点包含通过将图案化结构暴露于含有过渡金属前体或稀土金属前体的气体簇离子束而形成的熔融金属含有层。
-
-
-
-
-
-
-
-
-
搜索结果
14 条记录 (耗时 0.025 秒)
