公开(公告)号：US08589629B2

公开(公告)日：2013-11-19

申请号：US12413124

申请日：2009-03-27

申请人： Jonathan Owen ,  Guhan Krishnan ,  Carl D. Dietz ,  Douglas Richard Beard ,  William K. Lewchuk ,  Alexander Branover

发明人： Jonathan Owen ,  Guhan Krishnan ,  Carl D. Dietz ,  Douglas Richard Beard ,  William K. Lewchuk ,  Alexander Branover

IPC分类号： G06F12/00

CPC分类号： G06F12/126 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/0888

摘要： A system and method for data allocation in a shared cache memory of a computing system are contemplated. Each cache way of a shared set-associative cache is accessible to multiple sources, such as one or more processor cores, a graphics processing unit (GPU), an input/output (I/O) device, or multiple different software threads. A shared cache controller enables or disables access separately to each of the cache ways based upon the corresponding source of a received memory request. One or more configuration and status registers (CSRs) store encoded values used to alter accessibility to each of the shared cache ways. The control of the accessibility of the shared cache ways via altering stored values in the CSRs may be used to create a pseudo-RAM structure within the shared cache and to progressively reduce the size of the shared cache during a power-down sequence while the shared cache continues operation.

摘要翻译： 预期在计算系统的共享高速缓冲存储器中进行数据分配的系统和方法。 共享组相关高速缓存的每个缓存方式可以被多个源访问，诸如一个或多个处理器核，图形处理单元（GPU），输入/输出（I / O）设备或多个不同的软件线程。 共享高速缓存控制器基于所接收的存储器请求的相应源，启用或禁用对每个高速缓存路径的访问。 一个或多个配置和状态寄存器（CSR）存储用于改变对每个共享缓存方式的可访问性的编码值。 可以通过改变CSR中的存储值来控制共享缓存方式的可访问性，以在共享高速缓存内创建伪RAM结构，并且在断电序列期间逐渐减小共享高速缓存的大小，而共享高速缓存共享 缓存继续运行。

公开(公告)号：US20100250856A1

公开(公告)日：2010-09-30

申请号：US12413124

申请日：2009-03-27

申请人： Jonathan Owen ,  Guhan Krishnan ,  Carl D. Dietz ,  Douglas Richard Beard ,  William K. Lewchuk ,  Alexander Branover

发明人： Jonathan Owen ,  Guhan Krishnan ,  Carl D. Dietz ,  Douglas Richard Beard ,  William K. Lewchuk ,  Alexander Branover

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/126 ,  G06F12/0804 ,  G06F12/084 ,  G06F12/0888

摘要： A system and method for data allocation in a shared cache memory of a computing system are contemplated. Each cache way of a shared set-associative cache is accessible to multiple sources, such as one or more processor cores, a graphics processing unit (GPU), an input/output (I/O) device, or multiple different software threads. A shared cache controller enables or disables access separately to each of the cache ways based upon the corresponding source of a received memory request. One or more configuration and status registers (CSRs) store encoded values used to alter accessibility to each of the shared cache ways. The control of the accessibility of the shared cache ways via altering stored values in the CSRs may be used to create a pseudo-RAM structure within the shared cache and to progressively reduce the size of the shared cache during a power-down sequence while the shared cache continues operation.

摘要翻译： 预期在计算系统的共享高速缓冲存储器中进行数据分配的系统和方法。 共享组相关高速缓存的每个缓存方式可以被多个源访问，诸如一个或多个处理器核，图形处理单元（GPU），输入/输出（I / O）设备或多个不同的软件线程。 共享高速缓存控制器基于所接收的存储器请求的相应源，启用或禁用对每个高速缓存路径的访问。 一个或多个配置和状态寄存器（CSR）存储用于改变对每个共享缓存方式的可访问性的编码值。 可以通过改变CSR中的存储值来控制共享缓存方式的可访问性，以在共享高速缓存内创建伪RAM结构，并且在断电序列期间逐渐减小共享高速缓存的大小，而共享高速缓存共享 缓存继续运行。

公开(公告)号：US5608878A

公开(公告)日：1997-03-04

申请号：US316980

申请日：1994-10-03

申请人： Ravi K. Arimilli ,  John M. Kaiser ,  William K. Lewchuk ,  Michael S. Allen

发明人： Ravi K. Arimilli ,  John M. Kaiser ,  William K. Lewchuk ,  Michael S. Allen

IPC分类号： G06F12/08 ,  G06F13/00

CPC分类号： G06F12/0831

摘要： A multiprocessing system utilizes a bus protocol having two response windows. The first response window is at a fixed latency from the transmission of a bus request and/or address, while the second response window, utilized for coherency reporting, is placed a configurable number of clock cycles after the bus request and address to allow for longer access, or snoop, times to perform a cache directory look-up within other bus devices. The first response window reports error or flow control and error status. Furthermore, a method had been described, which implements the reporting of response information in a flexible and high performance manner.

摘要翻译： 多处理系统利用具有两个响应窗口的总线协议。 第一响应窗口处于来自总线请求和/或地址传输的固定延迟时间，而用于一致性报告的第二响应窗口在总线请求和地址之后被放置成可配置数量的时钟周期，以允许更长时间 访问或窥探时间，以执行其他总线设备内的缓存目录查找。 第一个响应窗口报告错误或流量控制和错误状态。 此外，已经描述了以灵活和高性能的方式报告响应信息的方法。

公开(公告)号：US06430639B1

公开(公告)日：2002-08-06

申请号：US09339351

申请日：1999-06-23

申请人： Derrick R. Meyer ,  William K. Lewchuk

发明人： Derrick R. Meyer ,  William K. Lewchuk

IPC分类号： G06F1200

CPC分类号： G06F13/4004

摘要： A system and method for using a toggle command for setting and releasing a lock, i.e. a locktoggle. In an exemplary computer system, one or more processors are each coupled to a bus bridge through separate high speed connections, such as a pair of uni-directional address buses with respective source-synchronous clock lines and a bi-directional data bus with attendant source-synchronous clock lines. The locktoggle command is used to transmit both a lock request and an unlock request from a processor to a system coherency. point, e.g. the bus bridge. The system coherency point acknowledges when the lock has been established or released. While the lock is active, other processors are inhibited. from accessing at least the memory locations for which the lock was initiated. Locks are thus established at the system coherency point, which may advantageously allow for locking functionality in a non-shared bus system. The use of the locktoggle command may advantageously allow for the use of a single command code point, leaving other points available for other uses.

摘要翻译： 一种用于使用切换命令来设置和释放锁的系统和方法，即锁定。 在示例性计算机系统中，一个或多个处理器各自通过单独的高速连接耦合到总线桥，诸如具有各自的源同步时钟线的一对单向地址总线和具有伴随源的双向数据总线 同步时钟线。 locktoggle命令用于将锁定请求和解锁请求从处理器传输到系统一致性。 点，例如 公交大桥。 系统一致性点确认锁已经建立或释放。 当锁活动时，其他处理器被禁止。 至少访问锁启动的内存位置。 因此，锁在系统一致性点处建立，这可有利地允许在非共享总线系统中锁定功能。 使用locktoggle命令可以有利地允许使用单个命令代码点，使其他点可用于其他用途。

公开(公告)号：US06446189B1

公开(公告)日：2002-09-03

申请号：US09323321

申请日：1999-06-01

申请人： Gerald D. Zuraski, Jr. ,  Frederick D. Weber ,  William A. Hughes ,  William K. Lewchuk ,  Scott A. White ,  Michael T. Clark

发明人： Gerald D. Zuraski, Jr. ,  Frederick D. Weber ,  William A. Hughes ,  William K. Lewchuk ,  Scott A. White ,  Michael T. Clark

IPC分类号： G06F1200

CPC分类号： G06F12/1054

摘要： A processor is presented including a cache unit coupled to a bus interface unit (BIU). Address signal selection and masking functions are performed by circuitry within the BIU rather than within the cache unit, and physical addresses produced by the BIU are stored within the TLB. As a result, address signal selection and masking circuitry (e.g., a multiplexer and gating logic) are eliminated from a critical speed path within the cache unit, allowing the operational speed of the cache unit to be increased. The cache unit stores data items, and produces a data item corresponding to a received linear address. A translation lookaside buffer (TLB) within the cache unit stores multiple linear addresses and corresponding physical addresses. When a physical address corresponding to the received linear address is not found within the TLB, the cache unit passes the linear address to the BIU. The BIU includes address translation circuitry, a multiplexer, and gating logic, and returns the physical address corresponding to the linear address to the cache unit. The cache unit stores the physical address and the linear address within the TLB. The processor may also include a programmable control register and a microexecution unit. Upon detecting a change in state of an external masking signal, the microexecution unit may flush the contents of the TLB and modify a masking bit within the control register to reflect a new state of the masking signal.

摘要翻译： 呈现包括耦合到总线接口单元（BIU）的高速缓存单元的处理器。 地址信号选择和屏蔽功能由BIU内的电路而不是在高速缓存单元内执行，而由BIU生成的物理地址存储在TLB内。 结果，从高速缓存单元内的临界速度路径消除了地址信号选择和屏蔽电路（例如，多路复用器和门控逻辑），从而允许高速缓存单元的操作速度增加。 高速缓存单元存储数据项，并产生与所接收的线性地址对应的数据项。 缓存单元内的翻译后备缓冲器（TLB）存储多个线性地址和对应的物理地址。 当在TLB内没有找到与接收到的线性地址对应的物理地址时，高速缓存单元将线性地址传递给BIU。 BIU包括地址转换电路，多路复用器和门控逻辑，并将对应于线性地址的物理地址返回到高速缓存单元。 高速缓存单元存储TLB内的物理地址和线性地址。 处理器还可以包括可编程控制寄存器和微执行单元。 在检测到外部屏蔽信号的状态变化时，微执行单元可以刷新TLB的内容并修改控制寄存器内的屏蔽位以反映掩蔽信号的新状态。