公开(公告)号：US06430639B1

公开(公告)日：2002-08-06

申请号：US09339351

申请日：1999-06-23

申请人： Derrick R. Meyer ,  William K. Lewchuk

发明人： Derrick R. Meyer ,  William K. Lewchuk

IPC分类号： G06F1200

CPC分类号： G06F13/4004

摘要： A system and method for using a toggle command for setting and releasing a lock, i.e. a locktoggle. In an exemplary computer system, one or more processors are each coupled to a bus bridge through separate high speed connections, such as a pair of uni-directional address buses with respective source-synchronous clock lines and a bi-directional data bus with attendant source-synchronous clock lines. The locktoggle command is used to transmit both a lock request and an unlock request from a processor to a system coherency. point, e.g. the bus bridge. The system coherency point acknowledges when the lock has been established or released. While the lock is active, other processors are inhibited. from accessing at least the memory locations for which the lock was initiated. Locks are thus established at the system coherency point, which may advantageously allow for locking functionality in a non-shared bus system. The use of the locktoggle command may advantageously allow for the use of a single command code point, leaving other points available for other uses.

摘要翻译： 一种用于使用切换命令来设置和释放锁的系统和方法，即锁定。 在示例性计算机系统中，一个或多个处理器各自通过单独的高速连接耦合到总线桥，诸如具有各自的源同步时钟线的一对单向地址总线和具有伴随源的双向数据总线 同步时钟线。 locktoggle命令用于将锁定请求和解锁请求从处理器传输到系统一致性。 点，例如 公交大桥。 系统一致性点确认锁已经建立或释放。 当锁活动时，其他处理器被禁止。 至少访问锁启动的内存位置。 因此，锁在系统一致性点处建立，这可有利地允许在非共享总线系统中锁定功能。 使用locktoggle命令可以有利地允许使用单个命令代码点，使其他点可用于其他用途。

公开(公告)号：US07174467B1

公开(公告)日：2007-02-06

申请号：US10185171

申请日：2002-06-28

申请人： Frank P. Helms ,  Dale E. Gulick ,  Larry D. Hewitt ,  William A. Hughes ,  Paul C. Miranda ,  Derrick R. Meyer ,  Scott E. Swanstrom ,  Scott A. White

发明人： Frank P. Helms ,  Dale E. Gulick ,  Larry D. Hewitt ,  William A. Hughes ,  Paul C. Miranda ,  Derrick R. Meyer ,  Scott E. Swanstrom ,  Scott A. White

IPC分类号： G06F1/26 ,  G06F1/28 ,  G06F1/32

CPC分类号： G06F1/324 ,  G06F1/3228 ,  G06F1/3296 ,  G06F9/30083 ,  Y02D10/126 ,  Y02D10/172

摘要： A message based power management approach is utilized to provide power management for a multi-processor system. A power management message is received at one processor of the multi-processor system over an input/output communication link that provides input/output access for the processors of the multi-processor system. The power management message includes a power management field encoding a power management state for processors of the multi-processor system. The processor that received the power management message over the input/output communication link sends a power management message to other processors in the multi-processor system over one or more inter-processor communication links encoding the power management state.

摘要翻译： 利用基于消息的电源管理方法为多处理器系统提供电源管理。 在多处理器系统的一个处理器上通过输入/输出通信链路接收功率管理消息，该输入/输出通信链路为多处理器系统的处理器提供输入/输出接入。 电源管理消息包括对多处理器系统的处理器编码电源管理状态的电源管理字段。 通过输入/输出通信链路接收电力管理消息的处理器通过编码电源管理状态的一个或多个处理器间通信链路向多处理器系统中的其他处理器发送电源管理消息。

公开(公告)号：US07093105B2

公开(公告)日：2006-08-15

申请号：US10779503

申请日：2004-02-13

申请人： David Arthur James Webb, Jr. ,  James Keller ,  Derrick R. Meyer

发明人： David Arthur James Webb, Jr. ,  James Keller ,  Derrick R. Meyer

IPC分类号： G06F9/30

CPC分类号： G06F7/76 ,  G06F7/4824 ,  G06F7/508 ,  G06F7/535 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F2207/5352

摘要： A method and apparatus to allow program steps in an issue queue to be sent to the execution queue in a non program order provides reduced stall by allowing out of program order steps to be executed as needed resources become available. The method uses a modulus operation to preassign locations in the execution queues, and keep the entries in proper program order. The method employs an additional bit to represent the modules result (value) and may also utilize a load store number mapping memory to increase execution speed. With such an arrangement a computer system may decrease the lost performance due to waiting for required resource (i.e., memory or bus) availability for the current instruction, by issuing instructions for which the memory or bus resource is available even though the instruction is not the next one in the original program order. Thus the present invention allows memory reference instructions to issue as resources are available.

摘要翻译： 允许以非程序顺序将发布队列中的程序步骤发送到执行队列的方法和装置通过允许在需要的资源变得可用时执行程序顺序步骤来减少停止。 该方法使用模数运算来对执行队列中的位置进行预分配，并使条目保持正确的程序顺序。 该方法使用附加位来表示模块结果（值），并且还可以利用加载存储器号映射存储器来增加执行速度。 通过这样的布置，由于等待当前指令的所需资源（即，存储器或总线）可用性，计算机系统可以通过发出存储器或总线资源可用的指令来减少丢失的性能，即使该指令不是 下一个在原程序中。 因此，本发明允许存储器参考指令在资源可用时发布。

公开(公告)号：US07051218B1

公开(公告)日：2006-05-23

申请号：US10185195

申请日：2002-06-28

申请人： Dale E. Gulick ,  Frank P. Helms ,  Larry D. Hewitt ,  William A. Hughes ,  Paul C. Miranda ,  Derrick R. Meyer ,  Scott E. Swanstrom ,  Scott A. White

发明人： Dale E. Gulick ,  Frank P. Helms ,  Larry D. Hewitt ,  William A. Hughes ,  Paul C. Miranda ,  Derrick R. Meyer ,  Scott E. Swanstrom ,  Scott A. White

IPC分类号： G06F1/30 ,  G06F3/00 ,  G06F13/36

CPC分类号： G06F1/3209 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3253 ,  G06F1/3296 ,  G06F9/30083 ,  Y02D10/126 ,  Y02D10/151 ,  Y02D10/172

摘要： A message based power management system converts legacy signals used in power management, and other signals used to differentiate between power states, to messages sent over a communication link. A system message sent on a communication link includes a field encoding the level of power management for the device receiving the system message. Further, one or more additional signals, separate from the communication link, may be used to indicate when to take action after the power management message has been received.

摘要翻译： 基于消息的电力管理系统将用于电力管理的传统信号和用于区分电力状态的其他信号转换成通过通信链路发送的消息。 在通信链路上发送的系统消息包括对接收系统消息的设备的电源管理级进行编码的字段。 此外，与通信链路分离的一个或多个附加信号可以用于指示何时在接收到电力管理消息之后采取行动。

公开(公告)号：US06760838B2

公开(公告)日：2004-07-06

申请号：US09773763

申请日：2001-01-31

申请人： Jonathan M. Owen ,  Mark D. Hummel ,  Derrick R. Meyer

发明人： Jonathan M. Owen ,  Mark D. Hummel ,  Derrick R. Meyer

IPC分类号： G06F15177

CPC分类号： G06F15/177

摘要： A method for initializing a computing system comprising a plurality of devices which communicate on a communication link comprising a plurality of independent point-to-point links is provided, each of the point-to-point links interconnecting a respective pair of the plurality of devices. The method includes a link initialization procedure comprising initially configuring each respective pair of devices to communicate on the respective interconnecting link using common communication parameters, including a common frequency and a common link width. The link initialization procedure also may include an optimization procedure for determining maximum communication parameters for each interconnected pair of devices. If the maximum compatible parameters differ from the common parameters for any pair of devices, then the pair of devices may be reconfigured to communicate on the interconnecting link using the maximum compatible parameters. Once a communication capability has been established, the establishment of one or more communication fabrics for the computer system may be performed. This scheme includes designating a bootstrap processor, locating the boot ROM, establishing the manner in which the devices are interconnected, and defining routing directions for routing communications among the various devices in the computing system.

摘要翻译： 提供了一种用于初始化包括在包括多个独立点对点链路的通信链路上通信的多个设备的计算系统的方法，每个点对点链路互连所述多个设备中的相应对 。 该方法包括链路初始化过程，其包括首先使用包括公共频率和公共链路宽度的公共通信参数在每个互连链路上配置每个相应设备对进行通信。 链路初始化过程还可以包括用于确定每个互连的设备对的最大通信参数的优化过程。 如果最大兼容参数与任何设备对的公共参数不同，则可以使用最大兼容参数将该对设备重新配置为在互连链路上进行通信。 一旦建立了通信能力，就可以执行用于计算机系统的一个或多个通信结构的建立。 该方案包括指定引导处理器，定位引导ROM，建立设备互连的方式，以及定义用于在计算系统中的各种设备之间路由通信的路由选择方向。

公开(公告)号：US06738896B1

公开(公告)日：2004-05-18

申请号：US09495190

申请日：2000-01-31

申请人： David Arthur James Webb, Jr. ,  James Keller ,  Derrick R. Meyer

发明人： David Arthur James Webb, Jr. ,  James Keller ,  Derrick R. Meyer

IPC分类号： G06F930

CPC分类号： G06F7/76 ,  G06F7/4824 ,  G06F7/508 ,  G06F7/535 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F2207/5352

摘要： A method and apparatus to allow program steps in an issue queue to be sent to the execution queue in a non program order provides reduced stall by allowing out of program order steps to be executed as needed resources become available. The method uses a modulus operation to preassign locations in the execution queues, and keep the entries in proper program order. The method employs an additional bit to represent the modules result (valve) and may also utilize a load store number mapping memory to increase execution speed. With such an arrangement a computer system may decrease the lost performance due to waiting for required resource (i.e., memory or bus) availability for the current instruction, by issuing instructions for which the memory or bus resource is available even though the instruction is not the next one in the original program order. Thus the present invention allows memory reference instructions to issue as resources are available.

摘要翻译： 允许以非程序顺序将发布队列中的程序步骤发送到执行队列的方法和装置通过允许在需要的资源变得可用时执行程序顺序步骤来减少停止。 该方法使用模数运算来对执行队列中的位置进行预分配，并使条目保持正确的程序顺序。 该方法使用额外的位来表示模块结果（阀），并且还可以利用加载存储器号码映射存储器来增加执行速度。 通过这样的布置，由于等待当前指令的所需资源（即存储器或总线）可用性，计算机系统可以通过发出存储器或总线资源可用的指令来减少丢失的性能，即使该指令不是 下一个在原程序中。 因此，本发明允许存储器参考指令在资源可用时发布。

公开(公告)号：US06505261B1

公开(公告)日：2003-01-07

申请号：US09428633

申请日：1999-10-27

申请人： Derrick R. Meyer ,  Philip Enrique Madrid

发明人： Derrick R. Meyer ,  Philip Enrique Madrid

IPC分类号： G06F104

CPC分类号： G06F13/4059

摘要： A system and method for inputting a set of values, e.g. an operating frequency, using dual-use signal connections. In an exemplary computer system, one or more processors are each coupled to a bridge. The dual-use signal connections are used to input an operating frequency ratio to a processor. The operating frequency ratio may also be input to the bridge. Once the operation of the processor has been initialized, the dual-use signal connections may be used to output operating parameters of the processor. The use of the using dual-use signal connections may advantageously allow for the operating frequency ratio to be input to the processor without dedicated signal lines or pins.

摘要翻译： 一种用于输入一组值的系统和方法，例如 一个工作频率，使用两用信号连接。 在示例性计算机系统中，一个或多个处理器各自耦合到桥。 双用途信号连接用于向处理器输入工作频率比。 工作频率比也可以输入到桥。 一旦处理器的操作被初始化，则可以使用双重用途信号连接来输出处理器的操作参数。 使用使用双重用途信号连接可以有利地允许将工作频率比率输入到处理器，而无需专用信号线或引脚。

公开(公告)号：US06360314B1

公开(公告)日：2002-03-19

申请号：US09115186

申请日：1998-07-14

申请人： David Arthur James Webb, Jr. ,  James B. Keller ,  Derrick R. Meyer

发明人： David Arthur James Webb, Jr. ,  James B. Keller ,  Derrick R. Meyer

IPC分类号： G06F938

CPC分类号： G06F9/3834 ,  G06F9/3826

摘要： A bypass mechanism is disclosed for a computer system that executes load and store instructions out of order. The bypass mechanism compares the address of each issuing load instruction with a set of recent store instructions that have not yet updated memory. A match of the recent stores provides the load data instead of having to retrieve the data from memory. A store queue holds the recently issued stores. Each store queue entry and the issuing load includes a data size indicator. Subsequent to a data bypass, the data size indicator of the issuing load is compared against the data size indicator of the matching store queue entry. A trap is signaled when the data size indicator of the issuing load differs from the data size indicator of the matching store queue entry. The trap signal indicates that the data provided by the bypass mechanism was insufficient to satisfy the requirements of the load instruction. The bypass mechanism also operates in cases in which multiple prior stores to the same address are pending when a load that needs to read that address issues.

摘要翻译： 公开了一种用于执行装载和存储指令的计算机系统的旁路机构。 旁路机制将每个发布加载指令的地址与尚未更新内存的一组最近的存储指令进行比较。 最近的商店的匹配提供了加载数据，而不是从内存中检索数据。 商店队列持有最近发布的商店。 每个存储队列条目和发布加载包括数据大小指示符。 在数据旁路之后，将发布负载的数据大小指示符与匹配存储队列条目的数据大小指示符进行比较。 当发布负载的数据大小指示符与匹配的存储队列条目的数据大小指示符不同时，用信号通知陷阱。 陷阱信号表示旁路机构提供的数据不足以满足加载指令的要求。 在需要读取该地址的负载发生问题的情况下，旁路机制还可以在多个先前存储到同一地址的情况下进行操作。

公开(公告)号：US06253304B1

公开(公告)日：2001-06-26

申请号：US09224821

申请日：1999-01-04

申请人： Larry Hewitt ,  David Neal Suggs ,  Greg Smaus ,  Derrick R. Meyer

发明人： Larry Hewitt ,  David Neal Suggs ,  Greg Smaus ,  Derrick R. Meyer

IPC分类号： G06F946

CPC分类号： G06F9/4812

摘要： A first and a second local interrupt controller are disposed on a single integrated circuit. The first and second local interrupt controllers are coupled to controllably provide at least one interrupt request signal, respectively, to a first and second processor. An input/output (I/O) interrupt controller is also on the integrated circuit and coupled to receive an interrupt request from at least one input/output device. A communication circuit on the integrated circuit is coupled to the input/output interrupt controller and the first and second local interrupt controllers. The communication circuit provides for transfer of interrupt information between the first local interrupt controller, the second local interrupt controller and the input/output interrupt controller.

摘要翻译： 第一和第二局部中断控制器设置在单个集成电路上。 第一和第二局部中断控制器被耦合以可分别地向第一和第二处理器提供至少一个中断请求信号。 输入/输出（I / O）中断控制器也在集成电路上并被耦合以从至少一个输入/输出设备接收中断请求。 集成电路上的通信电路耦合到输入/输出中断控制器和第一和第二本地中断控制器。 通信电路提供第一局部中断控制器，第二局部中断控制器和输入/输出中断控制器之间的中断信息传输。

公开(公告)号：US07640315B1

公开(公告)日：2009-12-29

申请号：US09633087

申请日：2000-08-04

申请人： Derrick R. Meyer ,  Jonathan M. Owen ,  Mark D. Hummel ,  James B. Keller

发明人： Derrick R. Meyer ,  Jonathan M. Owen ,  Mark D. Hummel ,  James B. Keller

IPC分类号： G06F15/16

CPC分类号： G06F9/52

摘要： A messaging scheme to synchronize processes within a distributed memory multiprocessing computer system having two or more processing nodes interconnected using an interconnect structure of dual-unidirectional links. Each unidirectional link forms a point-to-point interconnect to transfer packetized information between two processing nodes. A lock acquisition request from a lock requesting node is placed into service by an arbitrating node when no previous lock requests are pending for service. The arbitrating node transmits a broadcast message to all nodes in the system, which, in turn, respond with a corresponding probe response message to inform the arbitrating node of cessation of issuance of new requests by the node sending the probe response message. The arbitrating node informs the lock requesting node of the requesting node's lock ownership by transmitting a target done message thereto. After completion of lock operations, the lock requesting node sends a lock release request to the arbitrating node, which, in turn, informs all processing nodes of lock release by transmitting another broadcast message within the system. The messaging protocol is completed when each node sends another probe response to the arbitrating node, which, in turn, sends a final target done message to the lock requesting node. Lock operations are performed without contention for system resources and without deadlocks among various processing nodes.

摘要翻译： 用于使具有使用双向单向链路的互连结构互连的两个或多个处理节点的分布式存储器多处理计算机系统内的进程同步的消息传递方案。 每个单向链路形成点对点互连以在两个处理节点之间传送分组信息。 当没有先前的锁定请求正在等待服务时，来自锁定请求节点的锁定获取请求被仲裁节点投入使用。 仲裁节点向系统中的所有节点发送广播消息，后者又响应相应的探测响应消息，通知仲裁节点发送探测响应消息的节点发出新请求。 仲裁节点通过向其发送目标完成消息来向锁请求节点通知请求节点的锁拥有权。 锁定操作完成后，锁定请求节点向仲裁节点发送锁定释放请求，仲裁节点又通过在系统内传送另一个广播消息来通知所有处理节点的锁定释放。 当每个节点向仲裁节点发送另一个探测响应时，完成消息协议，该仲裁节点又向锁定请求节点发送最终的目标完成消息。 执行锁定操作而不对系统资源产生争用，并且在各种处理节点之间没有死锁。