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公开(公告)号：US20090248989A1
公开(公告)日：2009-10-01
申请号：US12322807
申请日：2009-02-06
IPC分类号： G06F12/08
CPC分类号： G06F12/0826 , G06F12/0817
摘要： The invention has application in implementation of large Symmetric Multiprocessor Systems with a large number of nodes which include processing elements and associated cache memories. The illustrated embodiment of the invention provides for interconnection of a large number of multiprocessor nodes while reducing over the prior art the size of directories for tracking of memory coherency throughout the system. The embodiment incorporates within the memory controller of each node, directory information relating to the current locations of memory blocks which allows for elimination at a higher level in the node controllers of a larger volume of directory information relating to the location of memory blocks. This arrangement thus allows for more efficient implementation of very large multiprocessor computer systems.
摘要翻译： 本发明在具有大量节点的大型对称多处理器系统的实现中具有应用，其中包括处理元件和相关联的高速缓冲存储器。 本发明的所示实施例提供了大量多处理器节点的互连，同时在现有技术中减少了用于跟踪整个系统中的存储器一致性的目录的大小。 该实施例包括在每个节点的存储器控制器内，与存储块的当前位置相关的目录信息，其允许在节点控制器中的更高级别消除与存储块的位置相关的更大量的目录信息。 因此，这种布置允许更有效地实现非常大的多处理器计算机系统。
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公开(公告)号：US08930640B2
公开(公告)日：2015-01-06
申请号：US12322807
申请日：2009-02-06
CPC分类号： G06F12/0826 , G06F12/0817
摘要： The invention has application in implementation of large Symmetric Multiprocessor Systems with a large number of nodes which include processing elements and associated cache memories. The illustrated embodiment of the invention provides for interconnection of a large number of multiprocessor nodes while reducing over the prior art the size of directories for tracking of memory coherency throughout the system. The embodiment incorporates within the memory controller of each node, directory information relating to the current locations of memory blocks which allows for elimination at a higher level in the node controllers of a larger volume of directory information relating to the location of memory blocks. This arrangement thus allows for more efficient implementation of very large multiprocessor computer systems.
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公开(公告)号：US20110252264A1
公开(公告)日：2011-10-13
申请号：US13139989
申请日：2009-11-27
申请人： Angelo Solinas , Jordan Chicheportiche , Saïd Derradji , Jean-Jacques Pairault , Zoltan Menyhart , Sylvain Jeaugey , Philippe Couvee
发明人： Angelo Solinas , Jordan Chicheportiche , Saïd Derradji , Jean-Jacques Pairault , Zoltan Menyhart , Sylvain Jeaugey , Philippe Couvee
IPC分类号： G06F1/12
摘要： The present invention relates to a computer device with synchronization barrier. The device comprises a memory and a processing unit, capable of multiprocess processing on various processors and enabling the parallel execution of blocks by processes, said blocks being associated by groups in successive work steps, The device further comprises a hardware circuit with a usable address space to the memory, capable of receiving a call from each process indicating the end of execution of a current block, each call comprising data. The hardware circuit is arranged to authorize the execution of blocks of a later work step when all the blocks of the current work step have been executed. The accessibility to the address space is achieved by segments drawn from the data of each call.
摘要翻译： 本发明涉及具有同步屏障的计算机设备。 该设备包括存储器和处理单元，能够对各种处理器进行多处理处理，并且能够通过进程并行执行块，所述块在连续工作步骤中由组相关联。该设备还包括具有可用地址空间的硬件电路 到存储器，能够从每个进程接收到表示当前块的执行结束的呼叫，每个呼叫包括数据。 硬件电路被配置为当当前工作步骤的所有块都被执行时，授权执行后续工作步骤的块。 地址空间的可访问性是通过从每个调用的数据绘制的段来实现的。
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公开(公告)号：US09218222B2
公开(公告)日：2015-12-22
申请号：US13139989
申请日：2009-11-27
申请人： Angelo Solinas , Jordan Chicheportiche , Saïd Derradji , Jean-Jacques Pairault , Zoltan Menyhart , Sylvain Jeaugey , Philippe Couvee
发明人： Angelo Solinas , Jordan Chicheportiche , Saïd Derradji , Jean-Jacques Pairault , Zoltan Menyhart , Sylvain Jeaugey , Philippe Couvee
摘要： A computer device with synchronization barrier including a memory and a processing unit capable of multiprocess processing on various processors and enabling the parallel execution of blocks by processes, the blocks being associated by groups in successive work steps. The device further includes a hardware circuit with a usable address space to the memory, capable of receiving a call from each process indicating the end of execution of a current block, each call comprising data. The hardware circuit is arranged to authorize the execution of blocks of a later work step when all the blocks of the current work step have been executed. The accessibility to the address space is achieved by segments drawn from the data of each call.
摘要翻译： 一种具有同步屏障的计算机设备，包括存储器和能够对各种处理器进行多处理处理的处理单元，并且能够通过进程并行执行块，所述块在连续的工作步骤中被组关联。 该设备还包括具有到存储器的可用地址空间的硬件电路，能够接收来自每个进程的指示当前块的执行结束的呼叫，每个呼叫包括数据。 硬件电路被配置为当当前工作步骤的所有块都被执行时，授权执行后续工作步骤的块。 地址空间的可访问性是通过从每个调用的数据绘制的段来实现的。
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