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1.发明授权Program counter range comparator with equality, greater than, less than and non-equal detection modes 有权程序计数器范围比较器具有相等，大于，小于和不相等的检测模式公开(公告)号：US07610518B2
公开(公告)日：2009-10-27
申请号：US11467727
申请日：2006-08-28
申请人： Jose L. Flores , Lewis Nardini , Maria B. H. Gill
发明人： Jose L. Flores , Lewis Nardini , Maria B. H. Gill
CPC分类号： G06F11/3636 , G06F11/3656
摘要： An program counter address comparator includes two comparators comparing an input program counter address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit selection of either the program counter address bus or a secondary address bus. The reference addresses and control functions are enabled via central processing unit accessible memory mapped registers.
摘要翻译： 程序计数器地址比较器包括将输入程序计数器地址与各个参考地址进行比较的两个比较器。 比较器产生可选标准的匹配指示，例如大于，小于，等于，不等于，小于或等于，且大于或等于，并且可以选择性地链接。 输入多路复用器允许选择程序计数器地址总线或辅助地址总线。 参考地址和控制功能通过中央处理单元可访问存储器映射寄存器使能。
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2.发明授权Address range comparator for detection of multi-size memory accesses with data matching qualification and full or partial overlap 有权地址范围比较器，用于检测具有数据匹配限定和全部或部分重叠的多尺寸存储器访问公开(公告)号：US08655637B2
公开(公告)日：2014-02-18
申请号：US11566772
申请日：2006-12-05
申请人： Jose L. Flores , Lewis Nardini , Maria B. H. Gill
发明人： Jose L. Flores , Lewis Nardini , Maria B. H. Gill
IPC分类号： G06F9/455
CPC分类号： G06F11/3648 , G01R31/31703 , G01R31/31705 , G06F11/3656
摘要： An memory access address comparator includes two comparators comparing an input memory access address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as address size, full or partial overlap, greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit memory access address bus selection. The comparator output may be selectively dependent upon corresponding data matches. The reference addresses, comparison data and control functions are enabled via central processing unit accessible memory mapped registers.
摘要翻译： 存储器访问地址比较器包括将输入存储器访问地址与相应的参考地址进行比较的两个比较器。 比较器根据可选择的标准产生匹配指示，例如地址大小，全部或部分重叠，大于，小于，等于，不等于，小于等于并且大于或等于，并且可以是选择性地 链接。 输入多路复用器允许存储器访问地址总线选择。 比较器输出可以选择性地依赖于相应的数据匹配。 参考地址，比较数据和控制功能通过中央处理单元可访问存储器映射寄存器使能。
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3.发明授权Address range comparator for detection of multi size memory accesses with data matching qualification and full or partial overlap 有权地址范围比较器，用于检测具有数据匹配限定和全部或部分重叠的多尺寸存储器访问公开(公告)号：US07165018B2
公开(公告)日：2007-01-16
申请号：US10301887
申请日：2002-11-22
申请人： Jose L. Flores , Lewis Nardini , Maria B. H. Gill
发明人： Jose L. Flores , Lewis Nardini , Maria B. H. Gill
IPC分类号： G06F9/455
CPC分类号： G06F11/3648 , G01R31/31703 , G01R31/31705 , G06F11/3656
摘要： An memory access address comparator includes two comparators comparing an input memory access address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as address size, full or partial overlap, greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit memory access address bus selection. The comparator output may be selectively dependent upon corresponding data matches. The reference addresses, comparison data and control functions are enabled via central processing unit accessible memory mapped registers.
摘要翻译： 存储器访问地址比较器包括将输入存储器访问地址与相应的参考地址进行比较的两个比较器。 比较器根据可选择的标准产生匹配指示，例如地址大小，全部或部分重叠，大于，小于，等于，不等于，小于等于并且大于或等于，并且可以是选择性地 链接。 输入多路复用器允许存储器访问地址总线选择。 比较器输出可以选择性地依赖于相应的数据匹配。 参考地址，比较数据和控制功能通过中央处理单元可访问存储器映射寄存器使能。
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公开(公告)号：US07117398B2
公开(公告)日：2006-10-03
申请号：US10302192
申请日：2002-11-22
申请人： Jose L. Flores , Lewis Nardini , Maria B. H. Gill
发明人： Jose L. Flores , Lewis Nardini , Maria B. H. Gill
CPC分类号： G06F11/3636 , G06F11/3656
摘要： An program counter address comparator includes two comparators comparing an input program counter address with respective reference addresses. The comparators produce a match indication on selectable criteria, such as greater than, less than, equal to, not equal to, less than or equal to, and greater than or equal to, and can be selectively chained. Input multiplexers permit selection of either the program counter address bus or a secondary address bus. The reference addresses and control functions are enabled via central processing unit accessible memory mapped registers.
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公开(公告)号：US07127387B2
公开(公告)日：2006-10-24
申请号：US10302193
申请日：2002-11-22
CPC分类号： G06F11/3636 , G06F11/3656
摘要： A method of trace data compression receives trace data on a first port and a second port stores a prior data value. If trace data is received on only one port, then that trace data is transmitted as an indication of matching and non-matching sections between the current trace data and the stored data value and the non-matching sections of the current trace data on the one port. If trace data is received on both ports, then the first port trace data is transmitted relative to the prior stored value and the second port trace data is transmitted relative to the first port trace data. The stored prior data is reset to zero upon each initiation or termination of trace data on either port. The stored prior value is set to the second port value or the first port value if no second port value is received.
摘要翻译： 跟踪数据压缩的方法在第一端口上接收跟踪数据，而第二端口存储先前的数据值。 如果仅在一个端口上接收到跟踪数据，则该跟踪数据作为当前跟踪数据与存储的数据值之间的匹配和非匹配部分的指示以及当前跟踪数据的不匹配部分在一个端口上发送 港口。 如果在两个端口上都接收到跟踪数据，则相对于先前存储的值传输第一个端口跟踪数据，并且相对于第一个端口跟踪数据传输第二个端口跟踪数据。 在任一端口上的跟踪数据的每次启动或终止时，存储的先前数据被重置为零。 如果没有接收到第二个端口值，则将存储的先前值设置为第二个端口值或第一个端口值。
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公开(公告)号：US07716034B2
公开(公告)日：2010-05-11
申请号：US11467735
申请日：2006-08-28
CPC分类号： G06F11/3636 , G06F11/3656
摘要： A method of trace data compression receives trace data on a first port and a second port stores a prior data value. If trace data is received on only one port, then that trace data is transmitted as an indication of matching and non-matching sections between the current trace data and the stored data value and the non-matching sections of the current trace data on the one port. If trace data is received on both ports, then the first port trace data is transmitted relative to the prior stored value and the second port trace data is transmitted relative to the first port trace data. The stored prior data is reset to zero upon each initiation or termination of trace data on either port. The stored prior value is set to the second port value or the first port value if no second port value is received.
摘要翻译： 跟踪数据压缩的方法在第一端口上接收跟踪数据，而第二端口存储先前的数据值。 如果仅在一个端口上接收到跟踪数据，则该跟踪数据作为当前跟踪数据与存储的数据值之间的匹配和非匹配部分的指示以及当前跟踪数据的不匹配部分在一个端口上发送 港口。 如果在两个端口上都接收到跟踪数据，则相对于先前存储的值传输第一个端口跟踪数据，并且相对于第一个端口跟踪数据传输第二个端口跟踪数据。 在任一端口上的跟踪数据的每次启动或终止时，存储的先前数据被重置为零。 如果没有接收到第二个端口值，则将存储的先前值设置为第二个端口值或第一个端口值。
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7.发明授权Apparatus for alignment of data collected from multiple pipe stages with heterogeneous retention policies in an unprotected pipeline 有权用于将从多个管道段收集的数据与不受保护管道中的异质保留策略对齐的装置公开(公告)号：US06996735B2
公开(公告)日：2006-02-07
申请号：US10302236
申请日：2002-11-22
申请人： Jose L. Flores , Lewis Nardini
发明人： Jose L. Flores , Lewis Nardini
IPC分类号： G06F1/12
CPC分类号： G06F9/3869 , G06F9/321
摘要： A method and apparatus for trace data alignment for trace data generated during differing instruction pipeline stages selectively delays write data, memory access address and memory access control data zero, one or two pipeline stages dependent upon the memory access control data. Program counter data delayed by one clock cycle is delayed one pipeline stage if the next instruction is a new instruction. Program counter control data is also delayed one pipeline stage. The write data, memory access address, memory access control data, program counter data and program counter control data are further delayed a number of pipeline stages to align with read data. The program counter data holds if the pipeline is stalled. The write data, memory access address, memory access control data, program counter data and program counter control data holds in the multistage pipeline delay register if the pipeline is stalled.
摘要翻译： 用于在不同指令流水线阶段期间生成的跟踪数据的跟踪数据对准的方法和装置有选择地将写入数据，存储器访问地址和存储器访问控制数据零延迟，取决于存储器访问控制数据的一个或两个流水线级。 如果下一条指令是新指令，延迟一个时钟周期的程序计数器数据被延迟一个流水线级。 程序计数器控制数据也在一个流水线阶段被延迟。 写入数据，存储器访问地址，存储器访问控制数据，程序计数器数据和程序计数器控制数据进一步延迟了多个流水线级以与读取数据对准。 如果管道停滞，则程序计数器数据保持。 如果管道停滞，写入数据，存储器访问地址，存储器访问控制数据，程序计数器数据和程序计数器控制数据保持在多级流水线延迟寄存器中。
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8.发明授权Pipeline stage single cycle sliding alignment correction of memory read data with integrated data reordering for load and store instructions 有权流水线单周期滑动对准校正存储器读取数据，集成数据重新排序用于加载和存储指令公开(公告)号：US06889311B2
公开(公告)日：2005-05-03
申请号：US10302084
申请日：2002-11-22
申请人： Jose L. Flores , Lewis Nardini
发明人： Jose L. Flores , Lewis Nardini
CPC分类号： G06F9/3863 , G06F9/3867 , G06F11/3636
摘要： Trace data is aligned in a processor having an instruction pipeline by delaying write data and read data a predetermined number of clock cycles, selectively swapping both most significant write data and read data with least significant write data and read dependent upon memory access control data. The write and read data pass normally for even memory bank accesses and are swapped for odd memory bank accesses. Memory access control data, program counter data and program counter control data are similarly delayed. At least the read data and optionally all the data are held upon a pipeline stall.
摘要翻译： 在具有指令流水线的处理器中，跟踪数据通过延迟写入数据并以预定数量的时钟周期读取数据来对准具有指令流水线，有选择地将最重要的写入数据和读取数据与最低有效写入数据进行交换，并依赖于存储器访问控制数据进行读取。 写入和读取数据通常用于偶数存储体存取，并被交换用于奇数存储体存取。 存储器访问控制数据，程序计数器数据和程序计数器控制数据也被类似地延迟。 至少读取的数据和可选地所有的数据被保持在流水线停止。
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9.发明申请公开(公告)号：US20080120065A1
公开(公告)日：2008-05-22
申请号：US11839826
申请日：2007-08-16
申请人： Mayur Joshi , Anthony M. Hill , Jose L. Flores
发明人： Mayur Joshi , Anthony M. Hill , Jose L. Flores
CPC分类号： G01R31/2884 , G01R31/31727
摘要： This invention places plural ring oscillators on a semiconductor chip during manufacture. The respective oscillation frequencies of these ring oscillators are measured. The semiconductor chip is assigned a grade dependent upon the measured frequencies. The ring oscillators are disposed proximate to critical paths on the semiconductor chip and employ circuit types to model the critical path operation under as many the manufacturing variations as possible. A linearly fitted model of ring oscillator frequencies to critical path delays is constructed during characterization after manufacture.
摘要翻译： 本发明在制造过程中将多个环形振荡器放置在半导体芯片上。 测量这些环形振荡器的相应振荡频率。 半导体芯片的分配等级取决于测量的频率。 环形振荡器靠近半导体芯片上的关键路径设置，并且采用电路类型以在尽可能多的制造变化的范围内对关键路径操作进行建模。 在制造后的表征过程中，建立了环形振荡器频率到关键路径延迟的线性拟合模型。
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10.发明授权公开(公告)号：US08762087B2
公开(公告)日：2014-06-24
申请号：US11839826
申请日：2007-08-16
申请人： Mayur Joshi , Anthony M. Hill , Jose L. Flores
发明人： Mayur Joshi , Anthony M. Hill , Jose L. Flores
IPC分类号： G01R23/02
CPC分类号： G01R31/2884 , G01R31/31727
摘要： This invention places plural ring oscillators on a semiconductor chip during manufacture. The respective oscillation frequencies of these ring oscillators are measured. The semiconductor chip is assigned a grade dependent upon the measured frequencies. The ring oscillators are disposed proximate to critical paths on the semiconductor chip and employ circuit types to model the critical path operation under as many the manufacturing variations as possible. A linearly fitted model of ring oscillator frequencies to critical path delays is constructed during characterization after manufacture.
摘要翻译： 本发明在制造过程中将多个环形振荡器放置在半导体芯片上。 测量这些环形振荡器的相应振荡频率。 半导体芯片的分配等级取决于测量的频率。 环形振荡器靠近半导体芯片上的关键路径设置，并且采用电路类型以在尽可能多的制造变化的范围内对关键路径操作进行建模。 在制造后的表征过程中，建立了环形振荡器频率到关键路径延迟的线性拟合模型。
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