公开(公告)号：US07230313B2

公开(公告)日：2007-06-12

申请号：US10682323

申请日：2003-10-09

申请人： Joseph A. Yedinak ,  Dwayne S. Reichl ,  Bernard J. Czeck ,  Douglas J. Lange

发明人： Joseph A. Yedinak ,  Dwayne S. Reichl ,  Bernard J. Czeck ,  Douglas J. Lange

IPC分类号： H01L29/78

CPC分类号： H01L29/405 ,  H01L29/404 ,  H01L29/7395 ,  H01L29/7803

摘要： An integrated circuit includes a die having a device layer. An insulating layer is disposed over the device layer. A die street defines the outermost bounds of the die. A voltage divider network including a plurality of resistive elements derives a plurality of predetermined bias voltages. A field plate termination includes a plurality of field plates disposed on the oxide layer and are laterally spaced apart relative to each other and relative to the die street. Each of the plurality of field plates is electrically connected to a corresponding bias voltage. The bias voltage applied to a given field plate is determined by and increases with the proximity of that field plate relative to the die street.

摘要翻译： 集成电路包括具有器件层的管芯。 绝缘层设置在器件层上。 死街定义了模具的最外边界。 包括多个电阻元件的分压网络导出多个预定的偏置电压。 场板终端包括设置在氧化物层上并相对于彼此和相对于模具街道横向间隔开的多个场板。 多个场板中的每一个电连接到相应的偏置电压。 施加到给定场板的偏置电压由该场板相对于模具街道的接近度确定并随其增加。

公开(公告)号：US06906362B2

公开(公告)日：2005-06-14

申请号：US10315719

申请日：2002-12-10

申请人： Joseph A. Yedinak ,  Dwayne S. Reichl ,  Douglas J. Lange

发明人： Joseph A. Yedinak ,  Dwayne S. Reichl ,  Douglas J. Lange

IPC分类号： H01L29/739 ,  H01L29/80 ,  H01L31/112

CPC分类号： H01L29/7815 ,  H01L29/0696 ,  H01L29/7395

摘要： An integrated circuit die includes an active area having source dopants and contacts. An active area metal layer overlies the active area. A sense area is disposed on the die. A sense area metal layer overlies the sense area. A plurality of polysilicon gate stripes, polysilicon openings, and body stripes are disposed on the die, and extend in a continuous and uninterrupted manner from the active area into the sense area. A first region from which source dopants and contacts have been excluded surrounds a periphery of the sense area. An etched region is disposed over the first region, thereby separating and electrically isolating the sense area metal layer from the active area metal layer.

公开(公告)号：US07118951B2

公开(公告)日：2006-10-10

申请号：US11130794

申请日：2005-05-17

申请人： Joseph A. Yedinak ,  Dwayne S. Reichl ,  Douglas J. Lange

发明人： Joseph A. Yedinak ,  Dwayne S. Reichl ,  Douglas J. Lange

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L29/7815 ,  H01L29/0696 ,  H01L29/7395

摘要： An integrated circuit die includes an active area having source dopants and contacts. An active area metal layer overlies the active area. A sense area is disposed on the die. A sense area metal layer overlies the sense area. A plurality of polysilicon gate stripes, polysilicon openings, and body stripes are disposed on the die, and extend in a continuous and uninterrupted manner from the active area into the sense area. A first region from which source dopants and contacts have been excluded surrounds a periphery of the sense area. An etched region is disposed over the first region, thereby separating and electrically isolating the sense area metal layer from the active area metal layer.