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公开(公告)号:US12080707B2
公开(公告)日:2024-09-03
申请号:US18353907
申请日:2023-07-18
发明人: Tatsuya Naito
IPC分类号: H01L29/06 , H01L21/76 , H01L21/765 , H01L27/06 , H01L27/07 , H01L29/08 , H01L29/10 , H01L29/32 , H01L29/36 , H01L29/40 , H01L29/423 , H01L29/739 , H01L29/78 , H01L29/861
CPC分类号: H01L27/0635 , H01L21/76 , H01L21/765 , H01L27/0727 , H01L29/0696 , H01L29/0834 , H01L29/1095 , H01L29/32 , H01L29/36 , H01L29/404 , H01L29/405 , H01L29/407 , H01L29/4238 , H01L29/739 , H01L29/7397 , H01L29/78 , H01L29/8613 , H01L29/8611
摘要: A semiconductor device includes a semiconductor substrate having a first conductivity type drift region and a second conductivity type base region above the drift region, trench portions at an upper surface of the semiconductor substrate arrayed parallel to one another, each of them penetrating the base region, and mesa portions between respective trench portions. Among the mesa portions, at least one mesa portion includes a first conductivity type first semiconductor region having a higher concentration than the drift region, a second conductivity type second semiconductor region having a higher concentration than the base region, and a first conductivity type accumulation region between the base and drift regions and has a higher concentration than the drift region. The drift region does not extend above the accumulation region. In a longitudinal direction of the trench portions, the accumulation region extends beyond an end portion of the first semiconductor region.
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公开(公告)号:US20240014260A1
公开(公告)日:2024-01-11
申请号:US18332837
申请日:2023-06-12
发明人: Ru-Yi Su , Fu-Chih Yang , Chun Lin Tsai , Chih-Chang Cheng , Ruey-Hsin Liu
IPC分类号: H01L29/06 , H01L29/40 , H01L29/861 , H01L27/08 , H01L23/535 , H01L29/36 , H01L29/66
CPC分类号: H01L29/0646 , H01L29/404 , H01L29/8611 , H01L29/0623 , H01L29/063 , H01L28/20 , H01L27/0802 , H01L23/535 , H01L29/36 , H01L29/405 , H01L29/66136 , H01L29/7835
摘要: High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a substrate, a first doped region disposed in the substrate and doped with a first doping polarity, and a second doped region disposed in the substrate and horizontally outside the first doped region. The second doped region is doped with a second doping polarity opposite to the first doping polarity. The semiconductor device further includes a third doped region disposed completely within the first doped region. The third doped region is doped with the second doping polarity. The semiconductor device further includes a first isolation structure disposed over the first doped region and spaced apart from the second doped region and the third doped region, a second isolation structure disposed over the first doped region and the third doped region, and a resistor disposed over the first isolation structure.
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公开(公告)号:US20230411464A1
公开(公告)日:2023-12-21
申请号:US18035758
申请日:2021-11-01
发明人: Kaizhou TAN , Tian XIAO , Jiahao ZHANG , Xiaoquan LI , Pengfei WANG , Ying PEI , Guangbo LI , Yonghui YANG , Hequan JIANG , Peijian ZHANG , Sheng QIU , Liang CHEN , Wei CUI
CPC分类号: H01L29/405 , H01L29/407 , H01L29/7813 , H01L29/401 , H01L29/66734
摘要: A shared-dielectric MOSFET device with a resistive-field-plate and a preparation method are provided. In the shared-dielectric MOSFET device, the semi-insulating resistive-field-plate electrically connected to the trench gate structure and the drain structure is introduced in the drift region of the existing trench gate MOS devices, and when the trench gate structure controls the MOS channel to be turned on or turned off, the semi-insulating resistive-field-plate can adjust the doping concentration of the drift region, to modulate the conductance of the on-state drift region and the distribution of a off-state high-voltage blocking electric field, thereby obtaining a lower on-resistance. Meanwhile, in the preparation method of the present disclosure, the modern 2.5-dimensional processing technology based on deep trench etching is adopted, which is conducive to miniaturization designs and high density designs of the structure and is more suitable for the More than Moore development of modern integrated semiconductor devices.
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公开(公告)号:US20230275133A1
公开(公告)日:2023-08-31
申请号:US18066902
申请日:2022-12-15
IPC分类号: H01L29/40
CPC分类号: H01L29/405 , H01L29/401
摘要: A resistive field plate is arranged in a spiral shape in plan view so as to gradually approach an inner main electrode from an outer main electrode. The plurality of floating layers are arranged radially toward the low potential region around the high potential region in plan view. The resistive field plate is provided on the plurality of floating layers via an interlayer insulating film, and thus has a floating step reflecting a film thickness of each of the plurality of floating layers. That is, the resistive field plate is provided in such a manner that the floating step is repeatedly generated along the lapping direction.
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公开(公告)号:US20230178612A1
公开(公告)日:2023-06-08
申请号:US17999091
申请日:2021-03-31
发明人: KATSUHIKO TAKEUCHI
IPC分类号: H01L29/423 , H01L29/06 , H01L29/40 , H01L29/417 , H01L29/08 , H01L29/10 , H01L29/66 , H01L29/778 , H01L29/45
CPC分类号: H01L29/423 , H01L29/0692 , H01L29/405 , H01L29/41758 , H01L29/42316 , H01L29/08 , H01L29/10 , H01L29/401 , H01L29/66462 , H01L29/7786 , H01L29/452 , H01L23/3171
摘要: A semiconductor unit includes: a barrier layer including a first compound semiconductor; a channel layer including a second compound semiconductor, and bonded to the barrier layer at a first face; an insulation layer provided on a second face, of the barrier layer, that is on an opposite side of the first face, and having an opening section that exposes the barrier layer; a gate electrode provided to bury the opening section; a source electrode and a drain electrode that are provided on the second face of the barrier layer on both sides of the gate electrode with the gate electrode being interposed; and a material layer including a metal material or a semiconductor material, and provided in contact with the second face of the barrier layer between the gate electrode and the drain electrode.
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公开(公告)号:US20190189793A1
公开(公告)日:2019-06-20
申请号:US16273486
申请日:2019-02-12
发明人: CHIH-CHANG CHENG , FU-YU CHU , RUEY-HSIN LIU , KUANG-HSIN CHEN , CHIH-HSIN KO , SHIH-FEN HUANG
CPC分类号: H01L29/785 , H01L29/0649 , H01L29/0653 , H01L29/40 , H01L29/402 , H01L29/404 , H01L29/405 , H01L29/407 , H01L29/4175 , H01L29/66659 , H01L29/66681 , H01L29/6681 , H01L29/7816 , H01L29/7834 , H01L29/7835
摘要: A semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a gate structure formed over the substrate; a source region and a drain region formed in the substrate on either side of the gate structure, the source region and the drain region both having a first type of conductivity; and a field plate formed over the substrate between the gate structure and the drain region; wherein the field plate is coupled to the source region or a bulk electrode of the substrate. An associated method for fabricating the semiconductor structure is also disclosed.
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公开(公告)号:US20180331092A1
公开(公告)日:2018-11-15
申请号:US15543792
申请日:2016-09-30
IPC分类号: H01L27/02 , H01L29/06 , H01L29/866 , H01L23/528 , H01L29/739
CPC分类号: H01L27/0255 , H01L23/528 , H01L29/0615 , H01L29/0638 , H01L29/0649 , H01L29/0692 , H01L29/0696 , H01L29/0834 , H01L29/16 , H01L29/1608 , H01L29/2003 , H01L29/404 , H01L29/405 , H01L29/47 , H01L29/7391 , H01L29/7395 , H01L29/7808 , H01L29/861 , H01L29/866
摘要: A semiconductor device according to an embodiment includes: an insulating film formed on a voltage supporting region B; an overvoltage protection diode that includes an n-type semiconductor layer and a p-type semiconductor layer; conductor portions that are formed on the insulating film and are electrically connected to the overvoltage protection diode; and a high-potential portion arranged above the overvoltage protection diode via an insulating film. The p-type impurity concentration of the p-type semiconductor layer is lower than the n-type impurity concentration of the n-type semiconductor layer. In the reverse bias application state, the high-potential portion has a higher potential than a potential of the potential of the p-type semiconductor layer disposed directly under the high-potential portion.
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公开(公告)号:US20180182754A1
公开(公告)日:2018-06-28
申请号:US15900810
申请日:2018-02-21
发明人: Tatsuya NAITO
IPC分类号: H01L27/06 , H01L29/06 , H01L21/765 , H01L29/10 , H01L29/32
CPC分类号: H01L27/0635 , H01L21/76 , H01L21/765 , H01L27/0727 , H01L29/0696 , H01L29/0834 , H01L29/1095 , H01L29/32 , H01L29/36 , H01L29/404 , H01L29/405 , H01L29/407 , H01L29/4238 , H01L29/7397 , H01L29/8611 , H01L29/8613
摘要: A semiconductor device that allows easy hole extraction is provided. The semiconductor device includes: a semiconductor substrate having drift and base regions; a transistor portion formed in the semiconductor substrate; and a diode portion formed adjacent to the transistor portion and in the semiconductor substrate. In the transistor portion and the diode portion: a plurality of trench portions each arrayed along a predetermined array direction; and a plurality of mesa portions formed between respective trench portions are formed, among the plurality of mesa portions, at least one boundary mesa portion at a boundary between the transistor portion and the diode portion includes a contact region at an upper surface of the semiconductor substrate and having a concentration higher than that of the base region, and an area of the contact region at the boundary mesa portion is greater than an area of the contact region at another mesa portion.
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公开(公告)号:US20180114841A1
公开(公告)日:2018-04-26
申请号:US15782041
申请日:2017-10-12
IPC分类号: H01L29/40 , H01L29/06 , H01L29/732 , H01L29/739 , H01L29/74
CPC分类号: H01L29/405 , H01L29/0615 , H01L29/0619 , H01L29/0638 , H01L29/0696 , H01L29/404 , H01L29/7322 , H01L29/7391 , H01L29/7393 , H01L29/7395 , H01L29/74 , H01L29/7802 , H01L29/8611
摘要: A power semiconductor device is disclosed. In one example, the device comprises: a semiconductor body comprising a drift region, the drift region having dopants of a first conductivity type; an active region having at least one power cell; least partially into the semiconductor body; the at least one power cell being configured to conduct a load current between said terminals and to block a blocking voltage applied between said terminals; an edge that laterally terminates the semiconductor body; and a non-active termination structure arranged in between the edge and the active region. The termination structure comprises: at least one doped semiconductor region implemented in the semiconductor body; a conductor structure, and an ohmic path that electrically couples the conductor structure with an electrical potential of the first load terminal.
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公开(公告)号:US20180102424A1
公开(公告)日:2018-04-12
申请号:US15831112
申请日:2017-12-04
发明人: Yufei XIONG , Yunlong LIU , Hong YANG , Ho LIN , Tian Ping LV , Sheng ZOU , Qiu Ling JIA
IPC分类号: H01L29/739 , H01L21/3213 , H01L21/283 , H01L29/78 , H01L29/06
CPC分类号: H01L29/7397 , H01L21/283 , H01L21/3213 , H01L21/743 , H01L23/485 , H01L29/0623 , H01L29/0649 , H01L29/0653 , H01L29/1095 , H01L29/405 , H01L29/41766 , H01L29/7396 , H01L29/7398 , H01L29/7809 , H01L29/7813 , H01L29/7816 , H01L29/7827
摘要: A method of forming an IC including a power semiconductor device includes providing a substrate having an epi layer thereon with at least one transistor formed therein covered by a pre-metal dielectric (PMD) layer. Contact openings are etched from through the PMD into the epi layer to form a sinker trench extending to a first node of the device. A metal fill material is deposited to cover a sidewall and bottom of the sinker trench but not completely fill the sinker trench. A dielectric filler layer is deposited over the metal fill material to fill the sinker trench. An overburden region of the dielectric filler layer is removed stopping on a surface of the metal fill material in the overburden region to form a sinker contact. A patterned interconnect metal is formed providing a connection between the interconnect metal and metal fill material on the sidewall of the sinker trench.
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