-
公开(公告)号：US20140281137A1
公开(公告)日：2014-09-18
申请号：US13842006
申请日：2013-03-15
IPC分类号： G06F12/02
CPC分类号： G06F12/1425 , G06F9/30181 , G06F9/324 , G06F9/34 , G06F9/3814 , G06F9/3824 , G06F9/3861 , G06F2212/202
摘要： Access requests to access data operands from memory space designated as a type of execute-only memory are allowed to precede in response to determining that the operand access request was generated using a particular type of addressing mode.
摘要翻译： 允许从指定为只执行存储器类型的存储器空间访问数据操作数的访问请求，以响应于确定使用特定类型的寻址模式生成操作数访问请求。
-
公开(公告)号：US20090217011A1
公开(公告)日：2009-08-27
申请号：US12035969
申请日：2008-02-22
IPC分类号： G06F9/30
CPC分类号： G06F9/3861 , G06F9/30181
摘要： A processor begins exception processing in response to an exception event. Exception processing by the processor is halted during exception processing to facilitate debugging. The exception event can be a reset exception event or an interrupt exception event. Normal exception processing by the data processor can be resumed after debugging, or exception processing by the data processor can be aborted to allow the normal execution of instructions by the data processor to resume. An exception event can be selectively treated as an interrupt or a reset.
摘要翻译： 处理器响应于异常事件开始异常处理。 处理器异常处理在异常处理期间停止，以方便调试。 异常事件可以是复位异常事件或中断异常事件。 数据处理器的正常异常处理可以在调试后恢复，或者可以中止数据处理器的异常处理，以允许数据处理器恢复正常执行指令。 可以将异常事件选择性地视为中断或复位。
-
公开(公告)号：US09489316B2
公开(公告)日：2016-11-08
申请号：US13842006
申请日：2013-03-15
CPC分类号： G06F12/1425 , G06F9/30181 , G06F9/324 , G06F9/34 , G06F9/3814 , G06F9/3824 , G06F9/3861 , G06F2212/202
摘要： Access requests to access data operands from memory space designated as a type of execute-only memory are allowed to precede in response to determining that the operand access request was generated using a particular type of addressing mode.
摘要翻译： 允许从指定为只执行存储器类型的存储器空间访问数据操作数的访问请求，以响应于确定使用特定类型的寻址模式生成操作数访问请求。
-
公开(公告)号：US08417924B2
公开(公告)日：2013-04-09
申请号：US12035969
申请日：2008-02-22
IPC分类号： G06F9/44
CPC分类号： G06F9/3861 , G06F9/30181
摘要： A processor begins exception processing in response to an exception event. Exception processing by the processor is halted during exception processing to facilitate debugging. The exception event can be a reset exception event or an interrupt exception event. Normal exception processing by the data processor can be resumed after debugging, or exception processing by the data processor can be aborted to allow the normal execution of instructions by the data processor to resume. An exception event can be selectively treated as an interrupt or a reset.
摘要翻译： 处理器响应于异常事件开始异常处理。 处理器异常处理在异常处理期间停止，以方便调试。 异常事件可以是复位异常事件或中断异常事件。 数据处理器的正常异常处理可以在调试后恢复，或者可以中止数据处理器的异常处理，以允许数据处理器恢复正常执行指令。 可以将异常事件选择性地视为中断或复位。
-
5.发明授权Decryption systems and related methods for on-the-fly decryption within integrated circuits 有权解密系统及相关方法用于集成电路内的即时解密公开(公告)号：US09418246B2
公开(公告)日：2016-08-16
申请号：US14570706
申请日：2014-12-15
CPC分类号： G06F21/72 , G09C1/00 , H04L9/0637
摘要： Methods and systems are disclosed for on-the-fly decryption within an integrated circuit that adds zero additional cycles of latency within the overall decryption system performance. A decryption system within a processing system integrated circuit generates an encrypted counter value using an address while encrypted code associated with an encrypted software image is being obtained from an external memory using the address. The decryption system then uses the encrypted counter value to decrypt the encrypted code and to output decrypted code that can be further processed. A secret key and an encryption engine can be used to generate the encrypted counter value, and an exclusive-OR logic block can process the encrypted counter value and the encrypted code to generate the decrypted code. By pre-generating the encrypted counter value, additional cycle latency is avoided. Other similar data independent encryption/decryption techniques can also be used such as output feedback encryption/decryption modes.
摘要翻译： 公开了用于集成电路内的即时解密的方法和系统，其在整个解密系统性能中增加零个额外的延迟周期。 处理系统集成电路内的解密系统使用地址生成加密的计数器值，而使用该地址从外部存储器获得与加密的软件映像相关联的加密代码。 解密系统然后使用加密的计数器值来解密加密的代码并输出可进一步处理的解密代码。 可以使用秘密密钥和加密引擎来生成加密的计数器值，并且异或逻辑块可以处理加密的计数器值和加密的代码以生成解密的代码。 通过预生成加密的计数器值，避免了额外的周期延迟。 还可以使用其他类似的数据独立加密/解密技术，例如输出反馈加密/解密模式。
-
6.发明申请公开(公告)号：US20160173282A1
公开(公告)日：2016-06-16
申请号：US14570611
申请日：2014-12-15
CPC分类号： H04L9/0894 , H04L9/0822 , H04L2209/12
摘要： Methods and systems are disclosed for key management for on-the-fly hardware decryption within an integrated circuit. Encrypted information is received from an external memory and stored in an input buffer within the integrated circuit. The encrypted information includes one or more encrypted key blobs. The encrypted key blobs include one or more secret keys for encrypted code associated with one or more encrypted software images stored within the external memory. A key-encryption key (KEK) code for the encrypted key blobs is received from an internal data storage medium within the integrated circuit, and the KEK code is used to generate one or more key-encryption keys (KEKs). A decryption system then decrypts the encrypted key blobs using the KEKs to obtain the secret keys, and the decryption system decrypts the encrypted code using the secret keys. The resulting decrypted software code is then available for further processing.
摘要翻译： 公开了用于集成电路内的即时硬件解密的密钥管理的方法和系统。 从外部存储器接收加密信息并存储在集成电路内的输入缓冲器中。 加密的信息包括一个或多个加密的密钥块。 加密的密钥块包括用于与存储在外部存储器中的一个或多个加密软件图像相关联的加密代码的一个或多个秘密密钥。 从集成电路内的内部数据存储介质接收加密密钥块的密钥加密密钥（KEK）代码，并且使用KEK码生成一个或多个密钥加密密钥（KEK）。 然后，解密系统使用KEK解密加密的密钥块以获得秘密密钥，并且解密系统使用密钥对加密的密码进行解密。 所得到的解密的软件代码然后可用于进一步处理。
-
7.发明申请公开(公告)号：US20160171249A1
公开(公告)日：2016-06-16
申请号：US14570706
申请日：2014-12-15
CPC分类号： G06F21/72 , G09C1/00 , H04L9/0637
摘要： Methods and systems are disclosed for on-the-fly decryption within an integrated circuit that adds zero additional cycles of latency within the overall decryption system performance. A decryption system within a processing system integrated circuit generates an encrypted counter value using an address while encrypted code associated with an encrypted software image is being obtained from an external memory using the address. The decryption system then uses the encrypted counter value to decrypt the encrypted code and to output decrypted code that can be further processed. A secret key and an encryption engine can be used to generate the encrypted counter value, and an exclusive-OR logic block can process the encrypted counter value and the encrypted code to generate the decrypted code. By pre-generating the encrypted counter value, additional cycle latency is avoided. Other similar data independent encryption/decryption techniques can also be used such as output feedback encryption/decryption modes.
摘要翻译： 公开了用于集成电路内的即时解密的方法和系统，其在整个解密系统性能中增加零个额外的延迟周期。 处理系统集成电路内的解密系统使用地址生成加密的计数器值，而使用该地址从外部存储器获得与加密的软件映像相关联的加密代码。 解密系统然后使用加密的计数器值来解密加密的代码并输出可进一步处理的解密代码。 可以使用秘密密钥和加密引擎来生成加密的计数器值，并且异或逻辑块可以处理加密的计数器值和加密的代码以生成解密的代码。 通过预生成加密的计数器值，避免了额外的周期延迟。 还可以使用其他类似的数据独立加密/解密技术，例如输出反馈加密/解密模式。
-
公开(公告)号：US09729319B2
公开(公告)日：2017-08-08
申请号：US14570611
申请日：2014-12-15
CPC分类号： H04L9/0894 , H04L9/0822 , H04L2209/12
摘要： Methods and systems are disclosed for key management for on-the-fly hardware decryption within an integrated circuit. Encrypted information is received from an external memory and stored in an input buffer within the integrated circuit. The encrypted information includes one or more encrypted key blobs. The encrypted key blobs include one or more secret keys for encrypted code associated with one or more encrypted software images stored within the external memory. A key-encryption key (KEK) code for the encrypted key blobs is received from an internal data storage medium within the integrated circuit, and the KEK code is used to generate one or more key-encryption keys (KEKs). A decryption system then decrypts the encrypted key blobs using the KEKs to obtain the secret keys, and the decryption system decrypts the encrypted code using the secret keys. The resulting decrypted software code is then available for further processing.
-
9.发明授权Zero-cycle multi-state branch cache prediction data processing system and method thereof 失效零周期多状态分支缓存预测数据处理系统及其方法
公开(公告)号：US5592634A
公开(公告)日：1997-01-07
申请号：US242766
申请日：1994-05-16
CPC分类号： G06F9/3806 , G06F9/3844
摘要： A branch cache (40) has a plurality of storage levels (120, 122, 140, and/or 142) wherein at least two write registers (114 and 116) are used to perform a parallel write operation to at least two of the storage levels in the plurality of storage levels (120, 122, 140, and/or 142). The two write registers (114 and 116) are provided due to the fact that the branch cache 40 is implemented as a multi-state (typically five state--see FIG. 5) branch prediction unit having instruction folding. Instruction folding, as taught herein, allows a branch instruction which is predicted as being taken to be executed along with an instruction that precedes the branch in execution flow. The instruction which directly precedes the branch in execution flow is usually the instruction which is used to "fold" the branch. Effectively, this instruction folding allows branches, which are predicted as being taken, to be executed in zero clock cycles.
摘要翻译： 分支高速缓存（40）具有多个存储级别（120,122,140和/或142），其中至少两个写入寄存器（114和116）用于对存储器中的至少两个执行并行写入操作 多个存储级别（120,122,140和/或142）中的级别。 由于分支高速缓存40被实现为具有指令折叠的多状态（通常为五状态 - 图5）分支预测单元的事实，所以提供了两个写入寄存器（114和116）。 如本文所教导的指令折叠允许预测被执行的分支指令与执行流程中的分支之前的指令一起执行。 直接在执行流程中的分支之前的指令通常是用于“折叠”分支的指令。 有效地，该指令折叠允许在零时钟周期中执行被预测为被采取的分支。
-
-
-
-
-
-
-
-
搜索结果
9 条记录 (耗时 0.026 秒)
