公开(公告)号：US20160171249A1

公开(公告)日：2016-06-16

申请号：US14570706

申请日：2014-12-15

申请人： Joseph C. Circello ,  David J. Schimke ,  Mohit Arora ,  Lawrence L. Case ,  Rodney D. Ziolkowski

发明人： Joseph C. Circello ,  David J. Schimke ,  Mohit Arora ,  Lawrence L. Case ,  Rodney D. Ziolkowski

IPC分类号： G06F21/72 ,  H04L9/14 ,  H04L9/06

CPC分类号： G06F21/72 ,  G09C1/00 ,  H04L9/0637

摘要： Methods and systems are disclosed for on-the-fly decryption within an integrated circuit that adds zero additional cycles of latency within the overall decryption system performance. A decryption system within a processing system integrated circuit generates an encrypted counter value using an address while encrypted code associated with an encrypted software image is being obtained from an external memory using the address. The decryption system then uses the encrypted counter value to decrypt the encrypted code and to output decrypted code that can be further processed. A secret key and an encryption engine can be used to generate the encrypted counter value, and an exclusive-OR logic block can process the encrypted counter value and the encrypted code to generate the decrypted code. By pre-generating the encrypted counter value, additional cycle latency is avoided. Other similar data independent encryption/decryption techniques can also be used such as output feedback encryption/decryption modes.

摘要翻译： 公开了用于集成电路内的即时解密的方法和系统，其在整个解密系统性能中增加零个额外的延迟周期。 处理系统集成电路内的解密系统使用地址生成加密的计数器值，而使用该地址从外部存储器获得与加密的软件映像相关联的加密代码。 解密系统然后使用加密的计数器值来解密加密的代码并输出可进一步处理的解密代码。 可以使用秘密密钥和加密引擎来生成加密的计数器值，并且异或逻辑块可以处理加密的计数器值和加密的代码以生成解密的代码。 通过预生成加密的计数器值，避免了额外的周期延迟。 还可以使用其他类似的数据独立加密/解密技术，例如输出反馈加密/解密模式。

公开(公告)号：US09053325B2

公开(公告)日：2015-06-09

申请号：US13972933

申请日：2013-08-22

申请人： Mohit Arora ,  Rakesh Pandey

发明人： Mohit Arora ,  Rakesh Pandey

IPC分类号： G06F9/00 ,  G06F15/177 ,  G06F21/57 ,  H04L9/08

CPC分类号： G06F21/575 ,  H04L9/08 ,  H04L9/0863 ,  H04L9/3228

摘要： A decryption key management system includes a memory, a memory controller, a decryption engine, and an on-chip crypto-accelerator. A key blob and an encrypted code are stored in the memory. The memory controller fetches the key blob and stores it in a memory buffer. The decryption engine fetches the key blob and decrypts it using an OTP key to generate a decryption key. The decryption key is used to decrypt the encrypted code and generate a decrypted code.

摘要翻译： 解密密钥管理系统包括存储器，存储器控制器，解密引擎和片上加密加速器。 密钥块和加密代码存储在存储器中。 内存控制器提取密钥blob并将其存储在内存缓冲区中。 解密引擎使用OTP密钥取出密钥库并对其进行解密，以生成解密密钥。 解密密钥用于解密加密代码并生成解密码。

公开(公告)号：US20140353849A1

公开(公告)日：2014-12-04

申请号：US13905150

申请日：2013-05-30

申请人： Mohit Arora ,  Prashant Bhargava ,  Rishi Bhooshan

发明人： Mohit Arora ,  Prashant Bhargava ,  Rishi Bhooshan

IPC分类号： H01L23/00

CPC分类号： G06F21/86 ,  G06F2221/2143 ,  H01L23/573 ,  H01L2924/0002 ,  H01L2924/00

摘要： A system for generating a tamper detection signal indicating tampering with one or more circuits of an integrated circuit (IC) includes a tamper detection module, and wire-pairs connected to the tamper detection module and arranged in a winding configuration to form a wire-mesh. The wire-mesh is placed a predefined distance from the circuits. The tamper detection module generates and provides serial bit-streams to the wire-pairs for detecting a breach in the wire-mesh by an external probe.

摘要翻译： 用于产生表示篡改集成电路（IC）的一个或多个电路的篡改检测信号的系统包括篡改检测模块和连接到篡改检测模块并且以绕组配置布置以形成线网的线对 。 线网放置在与电路预定距离的位置。 篡改检测模块生成并提供串行比特流到线对，用于通过外部探针检测金属丝网中的突破。

公开(公告)号：US20090189894A1

公开(公告)日：2009-07-30

申请号：US12360844

申请日：2009-01-27

申请人： Julian Petrov ,  Juan Rivera ,  Tim Corbett ,  Mohit Arora

发明人： Julian Petrov ,  Juan Rivera ,  Tim Corbett ,  Mohit Arora

IPC分类号： G06T15/00

CPC分类号： G06T15/005 ,  G06F3/14 ,  G06F9/452 ,  G06F9/453 ,  G06F9/505 ,  G06F2209/509 ,  G06T19/00 ,  G06T2200/16 ,  G09G2340/02

摘要： Methods and systems for rendering three dimensional graphical data by intercepting a three dimensional graphics stream comprising three dimensional graphics commands generated by an application executing on a first computing machine, and then analyzing the characteristics associated with a remoting system to determine a location for rendering three dimensional data from the three dimensional graphics commands. The remoting system may comprise at least the first computing machine having a graphics rendering component, a second computing machine having a graphics rendering component and a network. Based on the analysis, a rendering location is determined and the application is induced to reinitialize a context for determining where to render three dimensional data. The three dimensional data is then rendered from the three dimensional graphics commands at the rendering location.

摘要翻译： 用于通过截取包括由第一计算机器上执行的应用程序生成的三维图形命令的三维图形流来再现三维图形数据的方法和系统，然后分析与远程系统相关联的特征，以确定渲染三维的位置 来自三维图形命令的数据。 遥控系统可以至少包括具有图形渲染组件的第一计算机，具有图形渲染组件和网络的第二计算机。 基于分析，确定呈现位置，并且引发应用程序来重新初始化上下文以确定在哪里呈现三维数据。 然后在渲染位置从三维图形命令渲染三维数据。

公开(公告)号：US20070075735A1

公开(公告)日：2007-04-05

申请号：US11242689

申请日：2005-10-04

申请人： Mohit Arora

发明人： Mohit Arora

IPC分类号： H03K19/177

CPC分类号： H03K19/17732 ,  H04L25/4908

摘要： A programmable logic device (PLD) with logic blocks and an embedded array block includes an x-bit (xB)/y-bit (yB) coder programmed into the embedded array block instead of into the logic blocks. An xB/yB coder programmed into an embedded array block of a PLD instead of into logic blocks utilizes less space in a PLD than an xB/yB encoder programmed into the logic blocks. Additionally, the xB/yB coder can operate without row or column crossing for efficient timing in high-speed applications. In an embodiment, the xB/yB coder is an 8B/10B coder. In a further embodiment, the 8B/10B coder comprises a 5B/6B encoder and a 3B/4B encoder.

摘要翻译： 具有逻辑块和嵌入式阵列块的可编程逻辑器件（PLD）包括编入嵌入式阵列块而不是逻辑块的x位（xB）/ y位（yB）编码器。 被编程到PLD的嵌入式阵列块而不是逻辑块中的xB / yB编码器比编码到逻辑块中的xB / yB编码器使用更少的PLD空间。 另外，xB / yB编码器可以在没有行或列交叉的情况下进行高速应用中的高效定时操作。 在一个实施例中，xB / yB编码器是8B / 10B编码器。 在另一实施例中，8B / 10B编码器包括5B / 6B编码器和3B / 4B编码器。

公开(公告)号：US20160173282A1

公开(公告)日：2016-06-16

申请号：US14570611

申请日：2014-12-15

申请人： Joseph C. Circello ,  David J. Schimke ,  Mohit Arora ,  Lawrence L. Case ,  Rodney D. Ziolkowski

发明人： Joseph C. Circello ,  David J. Schimke ,  Mohit Arora ,  Lawrence L. Case ,  Rodney D. Ziolkowski

IPC分类号： H04L9/08 ,  H04L9/06

CPC分类号： H04L9/0894 ,  H04L9/0822 ,  H04L2209/12

摘要： Methods and systems are disclosed for key management for on-the-fly hardware decryption within an integrated circuit. Encrypted information is received from an external memory and stored in an input buffer within the integrated circuit. The encrypted information includes one or more encrypted key blobs. The encrypted key blobs include one or more secret keys for encrypted code associated with one or more encrypted software images stored within the external memory. A key-encryption key (KEK) code for the encrypted key blobs is received from an internal data storage medium within the integrated circuit, and the KEK code is used to generate one or more key-encryption keys (KEKs). A decryption system then decrypts the encrypted key blobs using the KEKs to obtain the secret keys, and the decryption system decrypts the encrypted code using the secret keys. The resulting decrypted software code is then available for further processing.

摘要翻译： 公开了用于集成电路内的即时硬件解密的密钥管理的方法和系统。 从外部存储器接收加密信息并存储在集成电路内的输入缓冲器中。 加密的信息包括一个或多个加密的密钥块。 加密的密钥块包括用于与存储在外部存储器中的一个或多个加密软件图像相关联的加密代码的一个或多个秘密密钥。 从集成电路内的内部数据存储介质接收加密密钥块的密钥加密密钥（KEK）代码，并且使用KEK码生成一个或多个密钥加密密钥（KEK）。 然后，解密系统使用KEK解密加密的密钥块以获得秘密密钥，并且解密系统使用密钥对加密的密码进行解密。 所得到的解密的软件代码然后可用于进一步处理。

公开(公告)号：US20150186676A1

公开(公告)日：2015-07-02

申请号：US14145991

申请日：2014-01-01

申请人： Mohit Arora ,  Prashant Bhargava ,  Pradip Singh

发明人： Mohit Arora ,  Prashant Bhargava ,  Pradip Singh

IPC分类号： G06F21/64

CPC分类号： G06F21/725

摘要： A system for securing a real-time clock (RTC) of an electronic device includes a RTC counter that counts clock pulses of a RTC signal generated by a crystal oscillator, and a reference-time register that periodically stores a reference time value generated by a network-clock generator. A hash-value generator uses a predefined hash algorithm to generate first and second hash values based on the reference time value and the count of the RTC counter, respectively, at predetermined time intervals. A comparator compares the first and second hash values and generates a trigger signal when there is a mismatch.

摘要翻译： 用于保护电子设备的实时时钟（RTC）的系统包括对由晶体振荡器产生的RTC信号的时钟脉冲进行计数的RTC计数器和周期性地存储由 网络时钟发生器。 散列值生成器使用预定义的散列算法，以预定的时间间隔分别基于参考时间值和RTC计数器的计数来产生第一和第二散列值。 比较器比较第一和第二散列值，并且当存在不匹配时产生触发信号。

公开(公告)号：US08643410B1

公开(公告)日：2014-02-04

申请号：US13602199

申请日：2012-09-02

申请人： Prashant Bhargava ,  Mohit Arora ,  James R. Feddeler ,  Martin Mienkina

发明人： Prashant Bhargava ,  Mohit Arora ,  James R. Feddeler ,  Martin Mienkina

IPC分类号： H03K9/08

CPC分类号： G04F10/04 ,  H03L7/00

摘要： A system for compensating for variations in the frequency of an input clock signal having a first frequency includes a coarse counter that receives the input clock signal, counts a predetermined number of clock pulses of the input clock signal, and generates a coarse compensated clock signal having a second frequency. A first compensation module adjusts a clock pulse of the input clock signal based on a coarse compensation value. A residual period adjustment module accumulates a fine compensation value for each clock pulse of the coarse compensated clock signal. A fine counter operates at a third frequency of a fine clock signal, receives an adjusted delay value based on the accumulated fine compensation value, counts a number of fine clock pulses in each clock pulse of the coarse compensated clock signal, and generates a fine compensated clock signal having the second frequency.

摘要翻译： 用于补偿具有第一频率的输入时钟信号的频率变化的系统包括接收输入时钟信号的粗计数器，对输入时钟信号的预定数量的时钟脉冲进行计数，并产生具有 第二个频率。 第一补偿模块基于粗略的补偿值调整输入时钟信号的时钟脉冲。 残余周期调整模块对粗补偿时钟信号的每个时钟脉冲累积精细补偿值。 精细计数器以精细时钟信号的第三频率工作，基于累积的精细补偿值接收经调整的延迟值，对粗略补偿时钟信号的每个时钟脉冲中的精细时钟脉冲数进行计数，并产生精细补偿 时钟信号具有第二频率。

公开(公告)号：US08443224B2

公开(公告)日：2013-05-14

申请号：US12912780

申请日：2010-10-27

申请人： Prashant Bhargava ,  Mohit Arora

发明人： Prashant Bhargava ,  Mohit Arora

IPC分类号： G06F1/12 ,  G06F1/04 ,  G06F5/06

CPC分类号： G06F1/12

摘要： A circuit and method for synchronizing signals between asynchronous clock domains within digital electronic circuits decouples asynchronous clocks. The timing of the slower clock is used to prevent read and write to counters so that write signals from the fast clock domain can be directly used in the slower clock domain when the counters are not toggling. This feature removes the need for sampling and holding the data on the fast clock, which would require consume additional power and require additional circuit area.

摘要翻译： 用于在数字电子电路内的异步时钟域之间同步信号的电路和方法解耦异步时钟。 较慢时钟的定时用于防止读取和写入计数器，以便当计数器不切换时，来自快速时钟域的写入信号可以直接用于较慢时钟域。 该功能消除了对快速时钟采样和保持数据的需求，这将需要消耗额外的功率并需要额外的电路面积。

公开(公告)号：US20170327368A1

公开(公告)日：2017-11-16

申请号：US15162655

申请日：2016-05-24

申请人： Mohit Arora

发明人： Mohit Arora

IPC分类号： B67D1/08 ,  B67D1/14

CPC分类号： B67D1/0857 ,  B67D1/06 ,  B67D1/0867 ,  B67D1/14 ,  B67D1/1477

摘要： An apparatus for cooling a liquid being dispensed through a dispensing tower includes a replaceable cooling shank that sealingly engages a delivery nipple with one or more internally mounted annular seals. The replaceable cooling shank facilitates quick and cost efficient maintenance of the dispensing tower when the annular seals become worn.