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    SEMICONDUCTOR DEVICES WITH NON-PUNCH-THROUGH SEMICONDUCTOR CHANNELS HAVING ENHANCED CONDUCTION AND METHODS OF MAKING
    2.
    发明申请
    SEMICONDUCTOR DEVICES WITH NON-PUNCH-THROUGH SEMICONDUCTOR CHANNELS HAVING ENHANCED CONDUCTION AND METHODS OF MAKING 有权
    具有非穿孔半导体通道的半导体器件具有增强导电性和制造方法

    公开(公告)号：US20110217829A1

    公开(公告)日：2011-09-08

    申请号：US13108505

    申请日：2011-05-16

    申请人： Igor SANKIN ,  David C. SHERIDAN ,  Joseph Neil MERRETT

    发明人： Igor SANKIN ,  David C. SHERIDAN ,  Joseph Neil MERRETT

    IPC分类号： H01L21/205

    CPC分类号： H01L29/8083 ,  H01L29/1058 ,  H01L29/1608 ,  H01L29/7392 ,  H01L29/7722

    摘要： Semiconductor devices are described wherein current flow in the device is confined between the rectifying junctions (e.g., p-n junctions or metal-semiconductor junctions). The device provides non-punch-through behavior and enhanced current conduction capability. The devices can be power semiconductor devices as such as Junction Field-Effect Transistors (VJFETs), Static Induction Transistors (SITs), Junction Field Effect Thyristors, or JFET current limiters. The devices can be made in wide bandgap semiconductors such as silicon carbide (SiC). According to some embodiments, the device can be a normally-off SiC vertical junction field effect transistor. Methods of making the devices and circuits comprising the devices are also described.

    摘要翻译： 描述了半导体器件，其中器件中的电流限制在整流结（例如，p-n结或金属 - 半导体结）之间。 该器件提供非穿通性能和增强的电流传导能力。 这些器件可以是功率半导体器件，例如接地场效应晶体管（VJFET），静态感应晶体管（SIT），结场效应晶闸管或JFET限流器。 这些器件可以制成宽带隙半导体，如碳化硅（SiC）。 根据一些实施例，器件可以是常关的SiC垂直结场效应晶体管。 还描述了制造包括装置的装置和电路的方法。

    VERTICAL JUNCTION FIELD EFFECT TRANSISTOR WITH MESA TERMINATION AND METHOD OF MAKING THE SAME
    3.
    发明申请
    VERTICAL JUNCTION FIELD EFFECT TRANSISTOR WITH MESA TERMINATION AND METHOD OF MAKING THE SAME 审中-公开
    具有MESA终止的垂直连接场效应晶体管及其制造方法

    公开(公告)号：US20120309154A1

    公开(公告)日：2012-12-06

    申请号：US13587151

    申请日：2012-08-16

    申请人： Igor SANKIN ,  Joseph Neil MERRETT

    发明人： Igor SANKIN ,  Joseph Neil MERRETT

    IPC分类号： H01L21/336

    CPC分类号： H01L29/868 ,  H01L29/1608 ,  H01L29/872

    摘要： A vertical junction field effect transistor (VJFET) having a mesa termination and a method of making the device are described. The device includes: an n-type mesa on an n-type substrate; a plurality of raised n-type regions on the mesa comprising an upper n-type layer on a lower n-type layer; p-type regions between and adjacent the raised n-type regions and along a lower sidewall portion of the raised regions; dielectric material on the sidewalls of the raised regions, on the p-type regions and on the sidewalls of the mesa; and electrical contacts to the substrate (drain), p-type regions (gate) and the upper n-type layer (source). The device can be made in a wide-bandgap semiconductor material such as SiC. The method includes selectively etching through an n-type layer using a mask to form the raised regions and implanting p-type dopants into exposed surfaces of an underlying n-type layer using the mask.

    摘要翻译： 描述具有台面终止的垂直结型场效应晶体管（VJFET）和制造该器件的方法。 该装置包括：n型衬底上的n型台面; 在台面上的多个凸起的n型区域，包括在下n型层上的上n型层; 在凸起的n型区域之间和相邻的凸起区域的下侧壁部分之间的p型区域; 介电材料在凸起区域的侧壁上，在p型区域和台面的侧壁上; 和与基板（漏极），p型区域（gate）和上部n型层（源极）的电接触。 该器件可以制成诸如SiC的宽带隙半导体材料。 该方法包括使用掩模选择性地蚀刻n型层以形成凸起区域，并使用掩模将p型掺杂剂注入到下面的n型层的暴露表面中。

    SELF-ALIGNED TRENCH FIELD EFFECT TRANSISTORS WITH REGROWN GATES AND BIPOLAR JUNCTION TRANSISTORS WITH REGROWN BASE CONTACT REGIONS AND METHODS OF MAKING
    4.
    发明申请
    SELF-ALIGNED TRENCH FIELD EFFECT TRANSISTORS WITH REGROWN GATES AND BIPOLAR JUNCTION TRANSISTORS WITH REGROWN BASE CONTACT REGIONS AND METHODS OF MAKING 有权
    具有复位栅的自对准TRENCH场效应晶体管和带有基极接触区的双极晶体管晶体管和制造方法

    公开(公告)号：US20120305994A1

    公开(公告)日：2012-12-06

    申请号：US13585183

    申请日：2012-08-14

    申请人： Joseph Neil MERRETT ,  Igor SANKIN

    发明人： Joseph Neil MERRETT ,  Igor SANKIN

    IPC分类号： H01L29/808 ,  H01L29/732

    CPC分类号： H01L29/66068 ,  H01L29/732 ,  H01L29/808

    摘要： Junction field-effect transistors with vertical channels and self-aligned regrown gates and methods of making these devices are described. The methods use techniques to selectively grow and/or selectively remove semiconductor material to form a p-n junction gate along the sides of the channel and on the bottom of trenches separating source fingers. Methods of making bipolar junction transistors with self-aligned regrown base contact regions and methods of making these devices are also described. The semiconductor devices can be made in silicon carbide.

    摘要翻译： 描述了具有垂直沟道和自对准再生栅的结型场效应晶体管和制造这些器件的方法。 所述方法使用技术来选择性地生长和/或选择性地去除半导体材料，以沿着沟道的侧面和分离源极指的沟槽的底部形成p-n结栅极。 还描述了制造具有自对准重新生长的基极接触区域的双极结型晶体管的方法以及制造这些器件的方法。 半导体器件可以制成碳化硅。

    VERTICAL JUNCTION FIELD EFFECT TRANSISTOR WITH MESA TERMINATION AND METHOD OF MAKING THE SAME
    6.
    发明申请
    VERTICAL JUNCTION FIELD EFFECT TRANSISTOR WITH MESA TERMINATION AND METHOD OF MAKING THE SAME 有权
    具有MESA终止的垂直连接场效应晶体管及其制造方法

    公开(公告)号：US20080093637A1

    公开(公告)日：2008-04-24

    申请号：US11836994

    申请日：2007-08-10

    申请人： Igor SANKIN ,  Joseph MERRETT

    发明人： Igor SANKIN ,  Joseph MERRETT

    IPC分类号： H01L29/808 ,  H01L21/04

    CPC分类号： H01L29/868 ,  H01L29/1608 ,  H01L29/872

    摘要： A vertical junction field effect transistor (VJFET) having a mesa termination and a method of making the device are described. The device includes: an n-type mesa on an n-type substrate; a plurality of raised n-type regions on the mesa comprising an upper n-type layer on a lower n-type layer; p-type regions between and adjacent the raised n-type regions and along a lower sidewall portion of the raised regions; dielectric material on the sidewalls of the raised regions, on the p-type regions and on the sidewalls of the mesa; and electrical contacts to the substrate (drain), p-type regions (gate) and the upper n-type layer (source). The device can be made in a wide-bandgap semiconductor material such as SiC. The method includes selectively etching through an n-type layer using a mask to form the raised regions and implanting p-type dopants into exposed surfaces of an underlying n-type layer using the mask.

    摘要翻译： 描述具有台面终止的垂直结型场效应晶体管（VJFET）和制造该器件的方法。 该装置包括：n型衬底上的n型台面; 在台面上的多个凸起的n型区域，包括在下n型层上的上n型层; 在凸起的n型区域之间和相邻的凸起区域的下侧壁部分之间的p型区域; 介电材料在凸起区域的侧壁上，在p型区域和台面的侧壁上; 和与基板（漏极），p型区域（gate）和上部n型层（源极）的电接触。 该器件可以制成诸如SiC的宽带隙半导体材料。 该方法包括使用掩模选择性地蚀刻n型层以形成凸起区域，并使用掩模将p型掺杂剂注入到下面的n型层的暴露表面中。