公开(公告)号：US09947684B2

公开(公告)日：2018-04-17

申请号：US15241781

申请日：2016-08-19

申请人： Joyoung Park ,  Yong-Hyun Kwon ,  Jeongsoo Kim ,  Seok-Won Lee ,  Jinwoo Park ,  Oik Kwon ,  Seungpil Chung

发明人： Joyoung Park ,  Yong-Hyun Kwon ,  Jeongsoo Kim ,  Seok-Won Lee ,  Jinwoo Park ,  Oik Kwon ,  Seungpil Chung

IPC分类号： H01L27/11 ,  H01L27/11582 ,  H01L27/11568

CPC分类号： H01L27/11582 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/1157 ,  H01L27/11575

摘要： A semiconductor device includes a substrate including a cell region and a connection region. A stack is disposed on the substrate. A vertical channel structure penetrates the stack in the cell region. The stack includes electrode patterns and insulating patterns which are alternatingly and repeatedly stacked on the substrate. Each of the electrode patterns may extend in a first direction and include a pad portion. The pad portion is positioned in the connection region. The pad portion includes a first sidewall and a second sidewall that extend in the first direction on opposite sides of the pad portion. The first sidewall has a recessed portion that is recessed in a second direction crossing the first direction toward the second sidewall.

公开(公告)号：US09165941B2

公开(公告)日：2015-10-20

申请号：US14221601

申请日：2014-03-21

申请人： Songyi Yang ,  Seungpil Chung

发明人： Songyi Yang ,  Seungpil Chung

IPC分类号： H01L27/15 ,  H01L27/115 ,  H01L29/792

CPC分类号： H01L27/11582 ,  H01L27/11575 ,  H01L29/7926

摘要： A semiconductor memory device includes a substrate having a cell region and a peripheral region, a gate stack including a plurality of insulating layers and a plurality of gates alternately stacked on the cell region of the substrate, a stress buffer layer on the gate stack, a vertical channel that extends vertically through the gate stack and is electrically connected to the substrate, a memory layer wrapped around the vertical channel. A bit line electrically connected to the vertical channel may be provided on the gate stack. In a method of fabricating a semiconductor device, the buffer stress layer is formed directly on an upper insulating layer of a stack whose shape is altered to form the gate stack to inhibit warping of the substrate during fabrication of the device.

摘要翻译： 半导体存储器件包括具有单元区域和周边区域的衬底，包括多个绝缘层的栅极堆叠和交替堆叠在衬底的单元区域上的多个栅极，栅堆叠上的应力缓冲层， 垂直通道，其垂直延伸穿过栅极堆叠并且电连接到衬底，围绕垂直沟道缠绕的存储层。 电连接到垂直通道的位线可以设置在栅极堆叠上。 在制造半导体器件的方法中，缓冲应力层直接形成在其形状被改变以形成栅极堆叠的堆叠的上绝缘层上，以在器件的制造期间抑制衬底的翘曲。