公开(公告)号：US20120193705A1

公开(公告)日：2012-08-02

申请号：US13285291

申请日：2011-10-31

申请人： Ju-young Lim ,  Woon-kyung Lee ,  Jae-joo Shim ,  Hui-chang Moon ,  Sung-min Hwang

发明人： Ju-young Lim ,  Woon-kyung Lee ,  Jae-joo Shim ,  Hui-chang Moon ,  Sung-min Hwang

IPC分类号： H01L29/78 ,  H01L23/48

CPC分类号： G11C16/0483 ,  G11C5/025 ,  G11C5/063 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

摘要： A memory device includes a substrate having a cell array region defined therein. A dummy structure is disposed on or in the substrate near a boundary of the cell array region. The memory device also includes a vertical channel region disposed on the substrate in the cell array region. The memory device further includes a plurality of vertically stacked conductive gate lines with insulating layers interposed therebetween, the conductive gate lines and interposed insulating layers disposed laterally adjacent the vertical channel region and extending across the dummy structure, at least an uppermost one of the conductive gate lines and insulating layers having a surface variation at the crossing of the dummy structure configured to serve as a reference feature. The dummy structure may include a trench, and the surface variation may include an indentation overlying the trench.

摘要翻译： 存储器件包括其中限定有单元阵列区域的衬底。 在单元阵列区域的边界附近设置在基板上或基板上的虚设结构。 存储器件还包括设置在单元阵列区域中的衬底上的垂直沟道区域。 所述存储装置还包括多个垂直堆叠的导电栅极线，其间插入有绝缘层，所述导电栅极线和插入的绝缘层横向设置在所述垂直沟道区域的两侧并延伸穿过所述虚拟结构，所述至少一个所述导电栅极 线和绝缘层，其在被配置为用作参考特征的虚拟结构的交叉处具有表面变化。 虚拟结构可以包括沟槽，并且表面变化可以包括覆盖沟槽的凹陷。

公开(公告)号：US08836020B2

公开(公告)日：2014-09-16

申请号：US13285291

申请日：2011-10-31

申请人： Ju-young Lim ,  Woon-kyung Lee ,  Jae-joo Shim ,  Hui-chang Moon ,  Sung-min Hwang

发明人： Ju-young Lim ,  Woon-kyung Lee ,  Jae-joo Shim ,  Hui-chang Moon ,  Sung-min Hwang

IPC分类号： H01L27/108 ,  G11C5/02 ,  G11C5/06 ,  H01L27/115 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C5/025 ,  G11C5/063 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11582

摘要： A memory device includes a substrate having a cell array region defined therein. A dummy structure is disposed on or in the substrate near a boundary of the cell array region. The memory device also includes a vertical channel region disposed on the substrate in the cell array region. The memory device further includes a plurality of vertically stacked conductive gate lines with insulating layers interposed therebetween, the conductive gate lines and interposed insulating layers disposed laterally adjacent the vertical channel region and extending across the dummy structure, at least an uppermost one of the conductive gate lines and insulating layers having a surface variation at the crossing of the dummy structure configured to serve as a reference feature. The dummy structure may include a trench, and the surface variation may include an indentation overlying the trench.

摘要翻译： 存储器件包括其中限定有单元阵列区域的衬底。 在单元阵列区域的边界附近设置在基板上或基板上的虚设结构。 存储器件还包括设置在单元阵列区域中的衬底上的垂直沟道区域。 所述存储装置还包括多个垂直堆叠的导电栅极线，其间插入有绝缘层，所述导电栅极线和插入的绝缘层横向设置在所述垂直沟道区域的两侧并延伸穿过所述虚拟结构，所述至少一个所述导电栅极 线和绝缘层，其在被配置为用作参考特征的虚拟结构的交叉处具有表面变化。 虚拟结构可以包括沟槽，并且表面变化可以包括覆盖沟槽的凹陷。

公开(公告)号：US08133784B2

公开(公告)日：2012-03-13

申请号：US12588534

申请日：2009-10-19

申请人： Dew-ill Chung ,  Han-soo Kim ,  Jae-hun Jeong ,  Jin-soo Lim ,  Ki-hyun Kim ,  Ju-young Lim

发明人： Dew-ill Chung ,  Han-soo Kim ,  Jae-hun Jeong ,  Jin-soo Lim ,  Ki-hyun Kim ,  Ju-young Lim

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/8236

CPC分类号： H01L27/11578 ,  G11C16/0483 ,  H01L27/11582

摘要： A method of fabricating a non-volatile memory device according to an example embodiment may include etching a plurality of sacrificial films and insulation films to form a plurality of first openings that expose a plurality of first portions of a semiconductor substrate. A plurality of channel layers may be formed in the plurality of first openings so as to coat the plurality of first portions of the semiconductor substrate and side surfaces of the plurality of first openings. A plurality of insulation pillars may be formed on the plurality of channel layers so as to fill the plurality of first openings. The plurality of sacrificial films and insulation films may be further etched to form a plurality of second openings that expose a plurality of second portions of the semiconductor substrate. A plurality of side openings may be formed by removing the plurality of sacrificial films. A plurality of gate dielectric films may be formed on surfaces of the plurality of side openings. A plurality of gate electrodes may be formed on the plurality of gate dielectric films so as to fill the plurality of side openings.

摘要翻译： 根据示例性实施例的制造非易失性存储器件的方法可以包括蚀刻多个牺牲膜和绝缘膜以形成暴露半导体衬底的多个第一部分的多个第一开口。 可以在多个第一开口中形成多个沟道层，以便涂覆半导体衬底的多个第一部分和多个第一开口的侧表面。 可以在多个通道层上形成多个绝缘柱，以填充多个第一开口。 可以进一步蚀刻多个牺牲膜和绝缘膜以形成暴露半导体衬底的多个第二部分的多个第二开口。 可以通过去除多个牺牲膜来形成多个侧开口。 多个栅极电介质膜可以形成在多个侧面开口的表面上。 可以在多个栅极电介质膜上形成多个栅电极，以填充多个侧开口。

公开(公告)号：US20100248439A1

公开(公告)日：2010-09-30

申请号：US12588534

申请日：2009-10-19

申请人： Dew-Ill Chung ,  Han-soo Kim ,  Jae-hun Jeong ,  Jin-soo Lim ,  Ki-hyun Kim ,  Ju-young Lim

发明人： Dew-Ill Chung ,  Han-soo Kim ,  Jae-hun Jeong ,  Jin-soo Lim ,  Ki-hyun Kim ,  Ju-young Lim

IPC分类号： H01L21/336

CPC分类号： H01L27/11578 ,  G11C16/0483 ,  H01L27/11582

摘要： A method of fabricating a non-volatile memory device according to an example embodiment may include etching a plurality of sacrificial films and insulation films to form a plurality of first openings that expose a plurality of first portions of a semiconductor substrate. A plurality of channel layers may be formed in the plurality of first openings so as to coat the plurality of first portions of the semiconductor substrate and side surfaces of the plurality of first openings. A plurality of insulation pillars may be formed on the plurality of channel layers so as to fill the plurality of first openings. The plurality of sacrificial films and insulation films may be further etched to form a plurality of second openings that expose a plurality of second portions of the semiconductor substrate. A plurality of side openings may be formed by removing the plurality of sacrificial films. A plurality of gate dielectric films may be formed on surfaces of the plurality of side openings. A plurality of gate electrodes may be formed on the plurality of gate dielectric films so as to fill the plurality of side openings.

摘要翻译： 根据示例性实施例的制造非易失性存储器件的方法可以包括蚀刻多个牺牲膜和绝缘膜以形成暴露半导体衬底的多个第一部分的多个第一开口。 可以在多个第一开口中形成多个沟道层，以便涂覆半导体衬底的多个第一部分和多个第一开口的侧表面。 可以在多个通道层上形成多个绝缘柱，以填充多个第一开口。 可以进一步蚀刻多个牺牲膜和绝缘膜以形成暴露半导体衬底的多个第二部分的多个第二开口。 可以通过去除多个牺牲膜来形成多个侧开口。 多个栅极电介质膜可以形成在多个侧面开口的表面上。 可以在多个栅极电介质膜上形成多个栅电极，以填充多个侧开口。