公开(公告)号：US08522187B2

公开(公告)日：2013-08-27

申请号：US13311651

申请日：2011-12-06

申请人： Niels Fricke ,  Bernd Kemmler ,  Juergen Koehl ,  Karsten Muuss ,  Matthias Ringe

发明人： Niels Fricke ,  Bernd Kemmler ,  Juergen Koehl ,  Karsten Muuss ,  Matthias Ringe

IPC分类号： G06F9/455 ,  G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/78 ,  G06F2217/84

摘要： A method to optimize performance of an electric circuit design is disclosed. The method comprises providing for each circuit element of the electric circuit design available design parameter options; transforming the electric circuit design and the design parameter options into a linear programming model; determining a solution for the linear programming model; and based on the solution generating a list of circuit elements which design parameters need to be changed to a different option to achieve performance optimization.

摘要翻译： 公开了一种优化电路设计性能的方法。 该方法包括为电路的每个电路元件设计可用的设计参数选项; 将电路设计和设计参数选项转换为线性规划模型; 确定线性规划模型的解决方案; 并且基于产生电路元件列表的解决方案，其中设计参数需要改变为不同的选项以实现性能优化。

公开(公告)号：US20080216042A1

公开(公告)日：2008-09-04

申请号：US12032728

申请日：2008-02-18

申请人： Guenther Hutzl ,  Stephan Held ,  Juergen Koehl ,  Bernhard Korte ,  Jens Massberg ,  Matthias Ringe ,  Jens Vygen

发明人： Guenther Hutzl ,  Stephan Held ,  Juergen Koehl ,  Bernhard Korte ,  Jens Massberg ,  Matthias Ringe ,  Jens Vygen

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/62 ,  G06F2217/84

摘要： A method and program for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit. The clock tree and the sub-clock tree are preferably connected through one or multiple fixed circuits which must not be altered, cloned or removed. Several alternative implementations of the at least one logic structure are built and for each of the several alternative implementations data is stored. A set of configurations is built, each configuration comprising a combination of the one or several alternative implementations and each configuration satisfying the target arrival time windows at the complete set of sinks. A configuration is selected according to an evaluation of the data, preferably latency data, for constructing the configuration. No manual interaction is needed and a configuration with minimum latencies is provided.

摘要翻译： 一种用于设计具有给定的目标到达时间窗口的一组信宿中的电子电路，特别是时钟树和子时钟树的方法和程序，优选地在集成电路上。 时钟树和子时钟树优选通过一个或多个固定电路来连接，这些电路不能被改变，克隆或去除。 构建至少一个逻辑结构的几个替代实施方案，并且为了存储数据的几个备选实现中的每一个。 构建一组配置，每个配置包括一个或多个替代实现的组合，并且每个配置满足完整集合集合处的目标到达时间窗口。 根据用于构造配置的数据（优选等待时间数据）的评估来选择配置。 不需要手动交互，并提供具有最小延迟的配置。

公开(公告)号：US20060044932A1

公开(公告)日：2006-03-02

申请号：US11161159

申请日：2005-07-25

申请人： Andreas Arp ,  Juergen Koehl ,  Matthias Ringe

发明人： Andreas Arp ,  Juergen Koehl ,  Matthias Ringe

IPC分类号： G11C8/00

CPC分类号： G11C5/063 ,  G01R31/31723 ,  G06F17/5031 ,  G06F17/5077 ,  G11C29/025 ,  G11C29/50012

摘要： The present invention relates to a method for routing data paths in a semiconductor chip with a plurality of layers. The inventive method comprises the steps of wiring a launching clock path and a receiving clock path on one or more layers according to at least one predetermined condition, performing one or more timing tests for determining any critical paths, and determining a weight function for every layer of each critical path. Said weight function is defined as the difference between a property of the launching clock tree and the same property of the receiving clock tree on said layer. If said weight function is positive for any layer, the wiring of the data path is not allowed on said layer. Preferably the remaining layers are chosen in such a way that a local variation of the delay on said layer is minimal.

摘要翻译： 本发明涉及一种用于在具有多个层的半导体芯片中路由数据路径的方法。 本发明的方法包括以下步骤：根据至少一个预定条件在一个或多个层上布线发射时钟路径和接收时钟路径，执行用于确定任何关键路径的一个或多个定时测试，以及确定每个层的权重函数 的每个关键路径。 所述权重函数被定义为发射时钟树的属性与所述层上的接收时钟树的相同属性之间的差异。 如果任何层的权重函数为正，则所述层上不允许数据路径的布线。 优选地，以这样的方式选择剩余的层，即所述层上的延迟的局部变化是最小的。

公开(公告)号：US07844931B2

公开(公告)日：2010-11-30

申请号：US12032728

申请日：2008-02-18

申请人： Guenther Hutzl ,  Stephan Held ,  Juergen Koehl ,  Bernhard Korte ,  Jens Massberg ,  Matthias Ringe ,  Jens Vygen

发明人： Guenther Hutzl ,  Stephan Held ,  Juergen Koehl ,  Bernhard Korte ,  Jens Massberg ,  Matthias Ringe ,  Jens Vygen

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/62 ,  G06F2217/84

摘要： A method and program for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit. The clock tree and the sub-clock tree are preferably connected through one or multiple fixed circuits which must not be altered, cloned or removed. Several alternative implementations of the at least one logic structure are built and for each of the several alternative implementations data is stored. A set of configurations is built, each configuration comprising a combination of the one or several alternative implementations and each configuration satisfying the target arrival time windows at the complete set of sinks. A configuration is selected according to an evaluation of the data, preferably latency data, for constructing the configuration. No manual interaction is needed and a configuration with minimum latencies is provided.

摘要翻译： 一种用于设计具有给定的目标到达时间窗口的一组信宿中的电子电路，特别是时钟树和子时钟树的方法和程序，优选地在集成电路上。 时钟树和子时钟树优选通过一个或多个固定电路来连接，这些电路不能被改变，克隆或去除。 构建至少一个逻辑结构的几个替代实施方案，并且为了存储数据的几个备选实现中的每一个。 构建一组配置，每个配置包括一个或多个替代实现的组合，并且每个配置满足完整集合集合处的目标到达时间窗口。 根据用于构造配置的数据（优选等待时间数据）的评估来选择配置。 不需要手动交互，并提供具有最小延迟的配置。

公开(公告)号：US20080216043A1

公开(公告)日：2008-09-04

申请号：US12032734

申请日：2008-02-18

申请人： Guenther Hutzl ,  Stephan Held ,  Juergen Koehl ,  Bernhard Korte ,  Jens Massberg ,  Matthias Ringe ,  Jens Vygen

发明人： Guenther Hutzl ,  Stephan Held ,  Juergen Koehl ,  Bernhard Korte ,  Jens Massberg ,  Matthias Ringe ,  Jens Vygen

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/62 ,  G06F2217/84

摘要： A design structure for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit designed by an IC design house or other circuit design provider. The clock tree and the sub-clock tree are preferably connected through one or multiple fixed circuits which must not be altered, cloned or removed. Several alternative implementations of the at least one logic structure are built and for each of the several alternative implementations data is stored. A set of configurations is built, each configuration comprising a combination of the one or several alternative implementations and each configuration satisfying the target arrival time windows at the complete set of sinks. A configuration is selected according to an evaluation of the data, preferably latency data, for constructing the configuration. No manual interaction is needed and a configuration with minimum latencies is provided.

摘要翻译： 一种设计结构，用于设计具有给定目标到达时间窗口的一组接收器内的电子电路，特别是时钟树和子时钟树，优选地在由IC设计公司或其他电路设计提供商设计的集成电路上。 时钟树和子时钟树优选通过一个或多个固定电路来连接，这些电路不能被改变，克隆或去除。 构建至少一个逻辑结构的几个替代实施方案，并且为了存储数据的几个备选实现中的每一个。 构建一组配置，每个配置包括一个或多个替代实现的组合，并且每个配置满足完整集合集合处的目标到达时间窗口。 根据用于构造配置的数据（优选等待时间数据）的评估来选择配置。 不需要手动交互，并提供具有最小延迟的配置。

公开(公告)号：US20120144362A1

公开(公告)日：2012-06-07

申请号：US13311651

申请日：2011-12-06

申请人： Niels Fricke ,  Bernd Kemmler ,  Juergen Koehl ,  Karsten Muuss ,  Matthias Ringe

发明人： Niels Fricke ,  Bernd Kemmler ,  Juergen Koehl ,  Karsten Muuss ,  Matthias Ringe

IPC分类号： G06F17/50

CPC分类号： G06F17/505 ,  G06F2217/78 ,  G06F2217/84

摘要： A method to optimize performance of an electric circuit design is disclosed. The method comprises providing for each circuit element of the electric circuit design available design parameter options; transforming the electric circuit design and the design parameter options into a linear programming model; determining a solution for the linear programming model; and based on the solution generating a list of circuit elements which design parameters need to be changed to a different option to achieve performance optimization.

摘要翻译： 公开了一种优化电路设计性能的方法。 该方法包括为电路的每个电路元件设计可用的设计参数选项; 将电路设计和设计参数选项转换为线性规划模型; 确定线性规划模型的解决方案; 并且基于产生电路元件列表的解决方案，其中设计参数需要改变为不同的选项以实现性能优化。

公开(公告)号：US07526743B2

公开(公告)日：2009-04-28

申请号：US11161159

申请日：2005-07-25

申请人： Andreas Arp ,  Juergen Koehl ,  Matthias Ringe

发明人： Andreas Arp ,  Juergen Koehl ,  Matthias Ringe

IPC分类号： G06F17/50

CPC分类号： G11C5/063 ,  G01R31/31723 ,  G06F17/5031 ,  G06F17/5077 ,  G11C29/025 ,  G11C29/50012

摘要： The present invention relates to a method for routing data paths in a semiconductor chip with a plurality of layers. The inventive method comprises the steps of wiring a launching clock path and a receiving clock path on one or more layers according to at least one predetermined condition, performing one or more timing tests for determining any critical paths, and determining a weight function for every layer of each critical path. Said weight function is defined as the difference between a property of the launching clock tree and the same property of the receiving clock tree on said layer. If said weight function is positive for any layer, the wiring of the data path is not allowed on said layer. Preferably the remaining layers are chosen in such a way that a local variation of the delay on said layer is minimal.

摘要翻译： 本发明涉及一种用于在具有多个层的半导体芯片中路由数据路径的方法。 本发明的方法包括以下步骤：根据至少一个预定条件在一个或多个层上布线发射时钟路径和接收时钟路径，执行用于确定任何关键路径的一个或多个定时测试，以及确定每个层的权重函数 的每个关键路径。 所述权重函数被定义为发射时钟树的属性与所述层上的接收时钟树的相同属性之间的差异。 如果任何层的权重函数为正，则所述层上不允许数据路径的布线。 优选地，以这样的方式选择剩余的层，即所述层上的延迟的局部变化是最小的。

公开(公告)号：US07865855B2

公开(公告)日：2011-01-04

申请号：US11942744

申请日：2007-11-20

申请人： Juergen Koehl ,  Matthias Ringe

发明人： Juergen Koehl ,  Matthias Ringe

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5068

摘要： A method for generating a layout for an integrated circuit having a plurality of sinks and at least one source is disclosed. The source supplies a plurality of signals to the respective plurality of sinks. The method includes: identifying the source which supplies at least one of the respective sinks and having a negative slack; finding all sinks having a negative slack driven by the source; clustering the sinks according to timing and placement information read from a database, yielding a plurality of clusters of sinks, in which each cluster includes only a predetermined portion of the plurality of sinks; generating a plurality of clones associated with a respective one of the clusters of sinks; and coupling the clones to respective ones of the clusters of sinks yielding a second layout.

摘要翻译： 公开了一种用于产生具有多个接收器和至少一个源的集成电路的布局的方法。 源将多个信号提供给相应的多个汇。 该方法包括：识别供应相应汇的至少一个并且具有负的松弛的源; 找到由源驱动的负松弛的所有水槽; 根据从数据库读取的定时和放置信息来聚集汇，产生多个汇集群，其中每个群只包括多个汇的预定部分; 产生与所述汇的簇中的相应一个相关联的多个克隆; 并将克隆耦合到汇的各个簇中，产生第二布局。

公开(公告)号：US07886245B2

公开(公告)日：2011-02-08

申请号：US12032734

申请日：2008-02-18

申请人： Guenther Hutzl ,  Stephan Held ,  Juergen Koehl ,  Bernhard Korte ,  Jens Massberg ,  Matthias Ringe ,  Jens Vygen

发明人： Guenther Hutzl ,  Stephan Held ,  Juergen Koehl ,  Bernhard Korte ,  Jens Massberg ,  Matthias Ringe ,  Jens Vygen

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  G06F2217/62 ,  G06F2217/84

摘要： A design structure for designing an electronic circuit, especially a clock tree and a sub-clock tree, within a set of sinks with given target arrival time windows, preferably on an integrated circuit designed by an IC design house or other circuit design provider. The clock tree and the sub-clock tree are preferably connected through one or multiple fixed circuits which must not be altered, cloned or removed. Several alternative implementations of the at least one logic structure are built and for each of the several alternative implementations data is stored. A set of configurations is built, each configuration comprising a combination of the one or several alternative implementations and each configuration satisfying the target arrival time windows at the complete set of sinks. A configuration is selected according to an evaluation of the data, preferably latency data, for constructing the configuration. No manual interaction is needed and a configuration with minimum latencies is provided.

摘要翻译： 一种设计结构，用于设计具有给定目标到达时间窗口的一组接收器内的电子电路，特别是时钟树和子时钟树，优选地在由IC设计公司或其他电路设计提供商设计的集成电路上。 时钟树和子时钟树优选通过一个或多个固定电路来连接，这些电路不能被改变，克隆或去除。 构建至少一个逻辑结构的几个替代实施方案，并且为了存储数据的几个备选实现中的每一个。 构建一组配置，每个配置包括一个或多个替代实现的组合，并且每个配置满足完整集合集合处的目标到达时间窗口。 根据用于构造配置的数据（优选等待时间数据）的评估来选择配置。 不需要手动交互，并提供具有最小延迟的配置。

公开(公告)号：US20090064069A1

公开(公告)日：2009-03-05

申请号：US11942744

申请日：2007-11-20

申请人： Juergen Koehl ,  Matthias Ringe

发明人： Juergen Koehl ,  Matthias Ringe

IPC分类号： G06F17/50

CPC分类号： G06F17/5068

摘要： A method to provide optimization between synthesis and layout in modern integrated circuit design, the method includes the steps of: a) identifying (210) a source (10) which has at least one associated sink (30) having a negative slack, i.e. the source having a negative slack at its output; b) finding all sinks (30) driven by the identified source; and c) clustering (240) the sinks (30) according to timing and placement information read from a database, yielding a plurality of clusters (30a, 30b) of sinks, in which a cluster includes only a predetermined portion of the sinks.

摘要翻译： 一种在现代集成电路设计中提供合成和布局之间的优化的方法，所述方法包括以下步骤：a）识别（210）具有至少一个具有负松弛的相关联的接收器（30）的源（10），即， 源在其输出端具有负的松弛; b）查找由识别的来源驱动的所有水槽（30）; 以及c）根据从数据库读取的定时和放置信息来聚集（240）所述宿（30），从而产生宿的多个群集（30a，30b），其中群只包括所述宿的预定部分。