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公开(公告)号:US08183634B2
公开(公告)日:2012-05-22
申请号:US12536775
申请日:2009-08-06
申请人: Jun-Beom Park , Soon-Moon Jung , Han-Soo Kim , Jae-Hoon Jang , Jae-Hun Jeong , Jong-In Yun , Mi-So Hwang
发明人: Jun-Beom Park , Soon-Moon Jung , Han-Soo Kim , Jae-Hoon Jang , Jae-Hun Jeong , Jong-In Yun , Mi-So Hwang
IPC分类号: H01L27/12
CPC分类号: H01L27/0688 , H01L25/0657 , H01L27/11526 , H01L27/11529 , H01L27/11551 , H01L27/12 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要: A stack-type semiconductor device and a method of manufacturing the same are provided. The stack-type semiconductor device includes an insulation layer on a single-crystalline substrate, a contact plug penetrating the insulation layer to contact the single-crystalline substrate, an upper semiconductor pattern including an impurity region and a gate structure positioned between the impurity regions on the upper semiconductor pattern. An upper surface of the contact plug contacts a lower surface of the semiconductor pattern. An operation failure of the stack-type semiconductor device is reduced since the upper semiconductor pattern is electrically connected to the single-crystalline semiconductor substrate.
摘要翻译: 提供堆叠型半导体器件及其制造方法。 堆叠型半导体器件包括在单晶衬底上的绝缘层,穿透绝缘层以接触单晶衬底的接触插塞,包括位于杂质区之间的杂质区和栅结构的上半导体图案 上半导体图案。 接触插头的上表面接触半导体图案的下表面。 由于上半导体图形与单晶半导体衬底电连接,所以堆叠型半导体器件的操作故障减小。
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公开(公告)号:US20100032762A1
公开(公告)日:2010-02-11
申请号:US12536775
申请日:2009-08-06
申请人: Jun-Beom Park , Soon-Moon Jung , Han-Soo Kim , Jae-Hoon Jang , Jae-Hun Jeong , Jong-In Yun , Mi-So Hwang
发明人: Jun-Beom Park , Soon-Moon Jung , Han-Soo Kim , Jae-Hoon Jang , Jae-Hun Jeong , Jong-In Yun , Mi-So Hwang
IPC分类号: H01L27/12
CPC分类号: H01L27/0688 , H01L25/0657 , H01L27/11526 , H01L27/11529 , H01L27/11551 , H01L27/12 , H01L2225/06513 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要: A stack-type semiconductor device and a method of manufacturing the same are provided. The stack-type semiconductor device includes an insulation layer on a single-crystalline substrate, a contact plug penetrating the insulation layer to contact the single-crystalline substrate, an upper semiconductor pattern including an impurity region and a gate structure positioned between the impurity regions on the upper semiconductor pattern. An upper surface of the contact plug contacts a lower surface of the semiconductor pattern. An operation failure of the stack-type semiconductor device is reduced since the upper semiconductor pattern is electrically connected to the single-crystalline semiconductor substrate.
摘要翻译: 提供堆叠型半导体器件及其制造方法。 堆叠型半导体器件包括在单晶衬底上的绝缘层,穿透绝缘层以接触单晶衬底的接触插塞,包括位于杂质区之间的杂质区和栅结构的上半导体图案 上半导体图案。 接触插头的上表面接触半导体图案的下表面。 由于上半导体图形与单晶半导体衬底电连接,所以堆叠型半导体器件的操作故障减少。
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