公开(公告)号：US08183634B2

公开(公告)日：2012-05-22

申请号：US12536775

申请日：2009-08-06

申请人： Jun-Beom Park ,  Soon-Moon Jung ,  Han-Soo Kim ,  Jae-Hoon Jang ,  Jae-Hun Jeong ,  Jong-In Yun ,  Mi-So Hwang

发明人： Jun-Beom Park ,  Soon-Moon Jung ,  Han-Soo Kim ,  Jae-Hoon Jang ,  Jae-Hun Jeong ,  Jong-In Yun ,  Mi-So Hwang

IPC分类号： H01L27/12

CPC分类号： H01L27/0688 ,  H01L25/0657 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/12 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A stack-type semiconductor device and a method of manufacturing the same are provided. The stack-type semiconductor device includes an insulation layer on a single-crystalline substrate, a contact plug penetrating the insulation layer to contact the single-crystalline substrate, an upper semiconductor pattern including an impurity region and a gate structure positioned between the impurity regions on the upper semiconductor pattern. An upper surface of the contact plug contacts a lower surface of the semiconductor pattern. An operation failure of the stack-type semiconductor device is reduced since the upper semiconductor pattern is electrically connected to the single-crystalline semiconductor substrate.

摘要翻译： 提供堆叠型半导体器件及其制造方法。 堆叠型半导体器件包括在单晶衬底上的绝缘层，穿透绝缘层以接触单晶衬底的接触插塞，包括位于杂质区之间的杂质区和栅结构的上半导体图案 上半导体图案。 接触插头的上表面接触半导体图案的下表面。 由于上半导体图形与单晶半导体衬底电连接，所以堆叠型半导体器件的操作故障减小。

公开(公告)号：US20100032762A1

公开(公告)日：2010-02-11

申请号：US12536775

申请日：2009-08-06

申请人： Jun-Beom Park ,  Soon-Moon Jung ,  Han-Soo Kim ,  Jae-Hoon Jang ,  Jae-Hun Jeong ,  Jong-In Yun ,  Mi-So Hwang

发明人： Jun-Beom Park ,  Soon-Moon Jung ,  Han-Soo Kim ,  Jae-Hoon Jang ,  Jae-Hun Jeong ,  Jong-In Yun ,  Mi-So Hwang

IPC分类号： H01L27/12

CPC分类号： H01L27/0688 ,  H01L25/0657 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/12 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/00

摘要： A stack-type semiconductor device and a method of manufacturing the same are provided. The stack-type semiconductor device includes an insulation layer on a single-crystalline substrate, a contact plug penetrating the insulation layer to contact the single-crystalline substrate, an upper semiconductor pattern including an impurity region and a gate structure positioned between the impurity regions on the upper semiconductor pattern. An upper surface of the contact plug contacts a lower surface of the semiconductor pattern. An operation failure of the stack-type semiconductor device is reduced since the upper semiconductor pattern is electrically connected to the single-crystalline semiconductor substrate.

摘要翻译： 提供堆叠型半导体器件及其制造方法。 堆叠型半导体器件包括在单晶衬底上的绝缘层，穿透绝缘层以接触单晶衬底的接触插塞，包括位于杂质区之间的杂质区和栅结构的上半导体图案 上半导体图案。 接触插头的上表面接触半导体图案的下表面。 由于上半导体图形与单晶半导体衬底电连接，所以堆叠型半导体器件的操作故障减少。

公开(公告)号：US20090251962A1

公开(公告)日：2009-10-08

申请号：US12418821

申请日：2009-04-06

申请人： Jong-In Yun ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Han-Soo Kim ,  Jun-Beom Park ,  Jae-Hun Jeong

发明人： Jong-In Yun ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Han-Soo Kim ,  Jun-Beom Park ,  Jae-Hun Jeong

IPC分类号： G11C16/02 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/3418 ,  G11C16/3427 ,  H01L27/11551

摘要： A driving method of a three-dimensional memory device having a plurality of layers is provided. One of the layers is selected. A well of the selected layer is biased with a first well voltage. A word line voltage is applied to a selected word line of the selected layer. A well of an unselected layer is biased with a second well voltage higher than the first well voltage.

摘要翻译： 提供具有多个层的三维存储器件的驱动方法。 选择其中一个图层。 所选择的层的阱被第一阱电压偏置。 字线电压被施加到所选层的选定字线。 未选择的层的阱以比第一阱电压高的第二阱电压偏置。

公开(公告)号：US08004885B2

公开(公告)日：2011-08-23

申请号：US12418821

申请日：2009-04-06

申请人： Jong-In Yun ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Han-Soo Kim ,  Jun-Beom Park ,  Jae-Hun Jeong

发明人： Jong-In Yun ,  Jae-Hoon Jang ,  Soon-Moon Jung ,  Han-Soo Kim ,  Jun-Beom Park ,  Jae-Hun Jeong

IPC分类号： G11C16/04

CPC分类号： G11C16/3418 ,  G11C16/3427 ,  H01L27/11551

摘要： A driving method of a three-dimensional memory device having a plurality of layers is provided. One of the layers is selected. A well of the selected layer is biased with a first well voltage. A word line voltage is applied to a selected word line of the selected layer. A well of an unselected layer is biased with a second well voltage higher than the first well voltage.

摘要翻译： 提供具有多个层的三维存储器件的驱动方法。 选择其中一个图层。 所选择的层的阱被第一阱电压偏置。 字线电压被施加到所选层的选定字线。 未选择的层的阱以比第一阱电压高的第二阱电压偏置。

公开(公告)号：US08258517B2

公开(公告)日：2012-09-04

申请号：US12473055

申请日：2009-05-27

申请人： Jong-In Yun ,  Soon-Moon Jung ,  Han-Soo Kim ,  Hoo-Sung Cho ,  Jun-Beom Park ,  Jae-Hun Jeong

发明人： Jong-In Yun ,  Soon-Moon Jung ,  Han-Soo Kim ,  Hoo-Sung Cho ,  Jun-Beom Park ,  Jae-Hun Jeong

IPC分类号： H01L29/08

CPC分类号： H01L21/76224 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551

摘要： One embodiment exemplarily described herein can be generally characterized as a semiconductor device that includes a lower level device layer located over a semiconductor substrate, an interlayer insulating film located over the lower level device layer and an upper level device layer located over the interlayer insulating film. The lower level device layer may include a plurality of devices formed in the substrate. The upper level device layer may include a plurality of semiconductor patterns and at least one device formed in each of the plurality of semiconductor patterns. The plurality of semiconductor patterns may be electrically isolated from each other. Each of the plurality of semiconductor patterns may include at least one active portion and at least one body contact portion electrically connected to the at least one active portion.

摘要翻译： 本文示例性描述的一个实施方案通常可以表征为半导体器件，其包括位于半导体衬底上方的较低级器件层，位于下级器件层上的层间绝缘膜和位于层间绝缘膜上方的上位器件层。 下层器件层可以包括形成在衬底中的多个器件。 上级器件层可以包括多个半导体图案和形成在多个半导体图案中的每一个中的至少一个器件。 多个半导体图案可以彼此电隔离。 多个半导体图案中的每一个可以包括至少一个有效部分和至少一个电连接到该至少一个有效部分的主体接触部分。