公开(公告)号：US08551821B2

公开(公告)日：2013-10-08

申请号：US12960499

申请日：2010-12-04

申请人： Jung Hee Lee ,  Ki Sik Im ,  Jong Bong Ha

发明人： Jung Hee Lee ,  Ki Sik Im ,  Jong Bong Ha

IPC分类号： H01L21/335 ,  H01L21/8232 ,  H01L21/339 ,  H01L21/00 ,  H01L21/84

CPC分类号： H01L29/7787 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/517 ,  H01L29/66462

摘要： The present invention relates to an enhancement normally off nitride semiconductor device and a method of manufacturing the same. The method includes the steps of: forming a buffer layer on a substrate; forming a first nitride semiconductor layer on the buffer layer; forming a second nitride semiconductor layer on the first nitride semiconductor layer; etching a gate region above the second nitride semiconductor layer up to a predetermined depth of the first nitride semiconductor layer; forming an insulating film on the etched region and the second nitride semiconductor layer; patterning a source/drain region, etching the insulating film in the source/drain region, and forming electrodes in the source/drain region; and forming a gate electrode on the insulating film in the gate region. In this manner, the present invention provides a method of easily implementing a normally off enhancement semiconductor device by originally blocking 2DEG which is generated under a gate region. In addition, the present invention provides an enhancement normally off power semiconductor device with a simple and efficient driving circuit in a HEMT device.

摘要翻译： 本发明涉及一种增强常关氮化物半导体器件及其制造方法。 该方法包括以下步骤：在衬底上形成缓冲层; 在所述缓冲层上形成第一氮化物半导体层; 在所述第一氮化物半导体层上形成第二氮化物半导体层; 将第二氮化物半导体层上方的栅极区域蚀刻到第一氮化物半导体层的预定深度; 在蚀刻区域和第二氮化物半导体层上形成绝缘膜; 图案化源极/漏极区域，蚀刻源极/漏极区域中的绝缘膜，以及在源极/漏极区域中形成电极; 以及在栅极区域的绝缘膜上形成栅电极。 以这种方式，本发明提供了一种通过最初阻挡在栅极区域下产生的2DEG来容易地实现常关的增强型半导体器件的方法。 此外，本发明提供了一种在HEMT装置中具有简单有效的驱动电路的增强型常关功率半导体器件。

公开(公告)号：US20110140121A1

公开(公告)日：2011-06-16

申请号：US12960499

申请日：2010-12-04

申请人： JUNG HEE LEE ,  Ki Sik Im ,  Jong Bong Ha

发明人： JUNG HEE LEE ,  Ki Sik Im ,  Jong Bong Ha

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7787 ,  H01L29/1033 ,  H01L29/2003 ,  H01L29/517 ,  H01L29/66462

摘要： The present invention relates to an enhancement normally off nitride semiconductor device and a method of manufacturing the same. The method includes the steps of: forming a buffer layer on a substrate; forming a first nitride semiconductor layer on the buffer layer; forming a second nitride semiconductor layer on the first nitride semiconductor layer; etching a gate region above the second nitride semiconductor layer up to a predetermined depth of the first nitride semiconductor layer; forming an insulating film on the etched region and the second nitride semiconductor layer; patterning a source/drain region, etching the insulating film in the source/drain region, and forming electrodes in the source/drain region; and forming a gate electrode on the insulating film in the gate region. In this manner, the present invention provides a method of easily implementing a normally off enhancement semiconductor device by originally blocking 2DEG which is generated under a gate region. In addition, the present invention provides an enhancement normally off power semiconductor device with a simple and efficient driving circuit in a HEMT device.

摘要翻译： 本发明涉及一种增强常关氮化物半导体器件及其制造方法。 该方法包括以下步骤：在衬底上形成缓冲层; 在所述缓冲层上形成第一氮化物半导体层; 在所述第一氮化物半导体层上形成第二氮化物半导体层; 将第二氮化物半导体层上方的栅极区域蚀刻到第一氮化物半导体层的预定深度; 在蚀刻区域和第二氮化物半导体层上形成绝缘膜; 图案化源极/漏极区域，蚀刻源极/漏极区域中的绝缘膜，以及在源极/漏极区域中形成电极; 以及在栅极区域的绝缘膜上形成栅电极。 以这种方式，本发明提供了一种通过最初阻挡在栅极区域下产生的2DEG来容易地实现常关的增强型半导体器件的方法。 此外，本发明提供了一种在HEMT装置中具有简单有效的驱动电路的增强型常关功率半导体器件。

公开(公告)号：US20110057257A1

公开(公告)日：2011-03-10

申请号：US12654942

申请日：2010-01-08

申请人： Ki Yeol Park ,  Jung Hee Lee ,  Jong Bong Ha ,  Young Hwan Park ,  Woo Chul Jeon

发明人： Ki Yeol Park ,  Jung Hee Lee ,  Jong Bong Ha ,  Young Hwan Park ,  Woo Chul Jeon

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/4236 ,  H01L29/0657 ,  H01L29/2003 ,  H01L29/42376 ,  H01L29/66462 ,  H01L29/7787

摘要： The present invention provides a semiconductor device including: a base substrate; a semiconductor layer which is disposed on the base substrate and has a recess structure formed thereon; a gate structure covering the recess structure; a source electrode and a drain electrode which are disposed to be spaced apart from each other with respect to the gate structure interposed therebetween, on the semiconductor layer, wherein the semiconductor layer having an upper layer whose thickness is increased toward a first direction facing the drain electrode from the gate structure.

摘要翻译： 本发明提供一种半导体器件，包括：基底; 半导体层，其设置在所述基底基板上并具有形成在其上的凹部结构; 覆盖所述凹部结构的栅极结构; 源极电极和漏极电极，被设置成相对于介于它们之间的栅极结构彼此间隔开，在半导体层上，其中半导体层的厚度朝着面向漏极的第一方向上增加 电极从栅极结构。