公开(公告)号：US20120163794A1

公开(公告)日：2012-06-28

申请号：US13191983

申请日：2011-07-27

申请人： Jung Mao LIN ,  Ching Yuan Yang

发明人： Jung Mao LIN ,  Ching Yuan Yang

IPC分类号： H04J14/00 ,  H03K5/00

CPC分类号： H03K5/1534 ,  H04L7/0338

摘要： A level transition determination circuit includes a multi-phase clock generator, an oversampling unit, and a state detection circuit. The multi-phase clock generator is used for receiving an input clock signal and generating S×N clock signals, in which S and N are integers. Each clock signal is synchronized to the input clock signal and has a different delay time. The oversampling unit is used for performing N-times oversampling on M bit periods of the serial input data according to the clock signals, so as to generate M×N sampled values in parallel during the M bit periods. The state detection circuit is used for receiving (M×N)+1 sampled values and generating N detection signals by detecting level transitions between adjacent sampled values of the (M×N)+1 sampled values and the level transition results.

摘要翻译： 电平转换确定电路包括多相时钟发生器，过采样单元和状态检测电路。 多相时钟发生器用于接收输入时钟信号并产生S×N个时钟信号，其中S和N是整数。 每个时钟信号与输入时钟信号同步并具有不同的延迟时间。 过采样单元用于根据时钟信号对串行输入数据的M位周期进行N次过采样，以便在M位周期期间并行生成M×N采样值。 状态检测电路用于通过检测（M×N）+1采样值的相邻采样值和电平转换结果之间的电平转换来接收（M×N）+1采样值并产生N个检测信号。