公开(公告)号：US20130241661A1

公开(公告)日：2013-09-19

申请号：US13558360

申请日：2012-07-26

申请人： Chih-Hsiang Chang ,  Nai-Chen Cheng ,  Yu Lee ,  Ching-Yuan Yang

发明人： Chih-Hsiang Chang ,  Nai-Chen Cheng ,  Yu Lee ,  Ching-Yuan Yang

IPC分类号： H03B5/12

CPC分类号： H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1243 ,  H03B5/1296 ,  H03B19/14 ,  H03B27/00 ,  H03B2200/004 ,  H03B2200/0078 ,  H03B2201/0208 ,  H03L7/24

摘要： A voltage-controlled oscillator (VCO) module including a first VCO unit, a second VCO unit, and a matching circuit is provided. The first VCO unit includes a first terminal and a second terminal and generates a first oscillator signal. The second VCO unit is coupled to the first VCO unit and generates a second oscillator signal. The matching circuit is coupled between the first VCO unit and second VCO unit. The matching circuit includes a plurality of inductor modules respectively coupled between the first terminal of the first VCO unit and the second VCO unit, between the first terminal and the second terminal of the first VCO unit, and between the second terminal of the first VCO unit and the second VCO unit. Furthermore, a method for generating oscillator signals is also provided.

摘要翻译： 提供了包括第一VCO单元，第二VCO单元和匹配电路的压控振荡器（VCO）模块。 第一VCO单元包括第一端子和第二端子，并产生第一振荡器信号。 第二VCO单元耦合到第一VCO单元并产生第二振荡器信号。 匹配电路耦合在第一VCO单元和第二VCO单元之间。 匹配电路包括分别耦合在第一VCO单元的第一端和第二VCO单元之间的多个电感器模块，位于第一VCO单元的第一端子和第二端子之间，并且在第一VCO单元的第二端子之间 和第二个VCO单元。 此外，还提供了一种用于产生振荡器信号的方法。

公开(公告)号：US20110175651A1

公开(公告)日：2011-07-21

申请号：US12789424

申请日：2010-05-27

申请人： Chih-Hsiang CHANG ,  Jung-Mao Lin ,  Ching-Yuan Yang

发明人： Chih-Hsiang CHANG ,  Jung-Mao Lin ,  Ching-Yuan Yang

IPC分类号： H03B19/06 ,  H03B19/00

CPC分类号： H03B19/14

摘要： A frequency doubler receiving an in-phase oscillating signal and an inverse oscillating signal and generating an output signal oscillating at a multiplied frequency, accordingly. The frequency doubler has a first transistor, a second transistor, a first inductor and a second inductor. A first terminal of the first transistor and a first terminal of the second transistor are at a common voltage. The frequency doubler receives the in-phase oscillating signal and the inverse oscillating signal via control terminals of the first and second transistors. The first and second inductors couple a second terminal of the first transistor and a second terminal of the second transistor to an output terminal of the frequency doubler, respectively. The first and second inductors may be separate inductance devices or, in another case, be implemented by a symmetric inductor.

摘要翻译： 接收同相振荡信号的倍频器和反相振荡信号，并相应地产生以倍频振荡的输出信号。 倍频器具有第一晶体管，第二晶体管，第一电感器和第二电感器。 第一晶体管的第一端子和第二晶体管的第一端子处于公共电压。 倍频器通过第一和第二晶体管的控制端接收同相振荡信号和反相振荡信号。 第一和第二电感分别将第一晶体管的第二端子和第二晶体管的第二端子耦合到倍频器的输出端子。 第一和第二电感器可以是分离的电感器件，或者在另一种情况下可由对称电感器来实现。

公开(公告)号：US20110018645A1

公开(公告)日：2011-01-27

申请号：US12687891

申请日：2010-01-15

申请人： Chih-Hsiang Chang ,  Jung-Mao Lin ,  Ching-Yuan Yang

发明人： Chih-Hsiang Chang ,  Jung-Mao Lin ,  Ching-Yuan Yang

IPC分类号： H03B7/00 ,  H03B5/12

CPC分类号： H03B5/1228 ,  H03B5/1215 ,  H03B5/1221 ,  H03B5/1225 ,  H03B5/1253 ,  H03B5/1271 ,  H03B5/1296

摘要： A voltage controlled oscillator (VCO) includes a voltage controlled current source (VCCS), a negative resistance circuit (NRC), a first transformer, a second transformer, a first transistor and a second transistor. A current terminal of the VCCS receives a control voltage. First terminals of first and second current paths in the NRC are coupled to a current terminal of the VCCS. Primary sides of the first and the second transformers are respectively coupled to second terminals of the first and the second current paths. Secondary sides of the first and the second transformers are first and second output terminals of the VCO, respectively. First terminals of the first and the second transistor are respectively coupled to the secondary sides of the first and the second transformers. Control terminals of the first and the second transformers are respectively coupled to the primary sides of the first and the second transformers.

摘要翻译： 压控振荡器（VCO）包括压控电流源（VCCS），负电阻电路（NRC），第一变压器，第二变压器，第一晶体管和第二晶体管。 VCCS的电流端子接收控制电压。 NRC中的第一和第二电流路径的第一端子耦合到VCCS的电流端子。 第一和第二变压器的主侧分别耦合到第一和第二电流路径的第二端。 第一和第二变压器的次级侧分别是VCO的第一和第二输出端。 第一和第二晶体管的第一端分别耦合到第一和第二变压器的次级侧。 第一变压器和第二变压器的控制端子分别与第一变压器和第二变压器的一次侧接合。

公开(公告)号：US06754841B2

公开(公告)日：2004-06-22

申请号：US09842723

申请日：2001-04-27

申请人： Ching-Yuan Yang

发明人： Ching-Yuan Yang

IPC分类号： G06F104

CPC分类号： G06F1/10

摘要： A one-wire clock-skew compensating method and a circuit for the method are disclosed to solve the clock-skew problem in transmission of clock signals in a high-speed synchronous circuit such as of a CPU, hence the clock of a remote circuit and the clock input of the system can be accurately synchronized. The method is based on the principle of identical propagation delay on the forward and reverse paths at the two ends of one wire in transmission and receiving; a clock-deskew buffer composing a delay locked loop and a bidirectional buffer is provided in the front of the signal transmission end of the wire, while the other end of the wire has a bidirectional buffer too, hence signals are transmitted bidirectionally at the same time on the wire. When a signal is transmitted from the clock-deskew buffer to the latter bidirectional buffer through the forward and reverse paths, its arrival time is accurately controlled to avoid errors in dealing with signals due to phase difference between a reference clock and a remote clock as in conventional techniques.

摘要翻译： 公开了一种用于该方法的单线时钟偏移补偿方法和电路，以解决诸如CPU之类的高速同步电路中的时钟信号传输中的时钟偏移问题，因此远程电路的时钟和 系统的时钟输入可以精确同步。 该方法基于传输和接收中一根线两端的正向和反向路径上传播延迟相同的原理; 构成延迟锁定环和双向缓冲器的时钟 - 消隐缓冲器被提供在线的信号发送端的前方，而线的另一端也具有双向缓冲器，因此信号同时被双向传输 在线上 当通过正向和反向路径将信号从时钟 - 消隐缓冲器发送到后一个双向缓冲器时，其到达时间被精确地控制，以避免由于参考时钟和远程时钟之间的相位差而在处理信号时出现错误，如 常规技术。

公开(公告)号：US06334451B1

公开(公告)日：2002-01-01

申请号：US09692399

申请日：2000-10-19

申请人： Ching-yuan Yang

发明人： Ching-yuan Yang

IPC分类号： A46B1100

CPC分类号： A46B11/0027 ,  A46B2200/1066

摘要： A toothbrush with filling of toothpaste basically comprises a cylindrical toothpaste receiver having toothpaste therein, a toothbrush head with a guide passage therein, a turning end cap with a threaded rod and a squeezing block attaching to the threaded rod. When the end cap is turned, the squeezing block may be actuated to move forward or backward such that the toothpaste may be squeezed toward the toothbrush head to overflow over the bristles through the guide passage.

摘要翻译： 具有填充牙膏的牙刷基本上包括其中具有牙膏的圆柱形牙膏接收器，其中具有引导通道的牙刷头，具有螺纹杆的转动端盖和附接到螺纹杆的挤压块。 当端盖转动时，挤压块可以被致动以向前或向后移动，使得牙膏可以朝向牙刷头部挤压，以通过引导通道在刷毛上溢出。

公开(公告)号：US6094466A

公开(公告)日：2000-07-25

申请号：US782576

申请日：1997-01-10

申请人： Ching-Yuan Yang ,  Shen-Iuan Liu ,  Liang-Gee Chen

发明人： Ching-Yuan Yang ,  Shen-Iuan Liu ,  Liang-Gee Chen

IPC分类号： H03K23/44 ,  H03K23/66 ,  H03K21/00

CPC分类号： H03K23/44 ,  H03K23/667

摘要： The invention of the "high-frequency CMOS dual/multi modulus prescaler" is a new application in this field. Compared to other transistors which have CMOS technology, this invention has a greater potential for high frequency operations. Additionally, it has a low-power consumption property and can be easily integrated with CMOS technology. We propose a general construction of the prescaler which can be applied to dual-modulus prescaler. First, a divide-by-3/4 dual-modulus prescaler and a divide-by-4/5 one are presented. Consequently, a general dual-modulus prescaler is developed based on the same technique. Moreover, a general multi-modulus prescaler will also be achieved. The operating frequency can be up to 1 GHz for the proposed dual/multiple modulus prescalers which are fabricated in a 0.8-.mu.m SPDM CMOS technology.

摘要翻译： “高频CMOS双/多模预分频器”的发明是该领域的新应用。 与具有CMOS技术的其它晶体管相比，本发明对于高频操作具有更大的潜力。 此外，它具有低功耗特性，可以方便地与CMOS技术集成。 我们提出可以应用于双模预分频器的预分频器的一般结构。 首先，提出了3/4分频双模预分频器和4/5分频器。 因此，基于相同的技术开发了一般的双模预分频器。 此外，还将实现一般的多模预分频器。 对于以0.8μmSPDM CMOS技术制造的所提出的双/多模预分频器，工作频率可高达1GHz。

公开(公告)号：US5930322A

公开(公告)日：1999-07-27

申请号：US959025

申请日：1997-10-28

申请人： Ching-Yuan Yang ,  Shen-Iuan Liu

发明人： Ching-Yuan Yang ,  Shen-Iuan Liu

IPC分类号： H03K23/66 ,  H03K21/00

CPC分类号： H03K23/667

摘要： A divide-by-4/5 counter includes a half transparent register, a domino logic, a buffer, a divide-by-4 counter and a control circuit. The half transparent register includes first, second, and third NMOS and PMOS transistors and first and second inverters. The domino logic includes fourth PMOS and NMOS transistors and first and second switches. The buffer is connected to a drain of the fourth PMOS transistor for out putting a reference clock signal. The divide-by-4 counter includes two divide-by-2 counters to obtain a divide-by-2 clock signal and an output clock signal. The control circuit is connected to a control terminal of the second switch for outputting a control signal of the domino logic according to the divide-by-2 clock signal, the output clock signal and a divide-by-4/5 control signal.

摘要翻译： 4/5分频计数器包括半透明寄存器，多米诺骨牌逻辑，缓冲器，4分频计数器和控制电路。 半透明寄存器包括第一，第二和第三NMOS和PMOS晶体管以及第一和第二反相器。 多米诺骨牌包括第四PMOS和NMOS晶体管以及第一和第二开关。 缓冲器连接到第四PMOS晶体管的漏极，用于输出参考时钟信号。 4分频计数器包括两个除以2的计数器，以获得二分之一的时钟信号和输出时钟信号。 控制电路连接到第二开关的控制端，用于根据二分频时钟信号，输出时钟信号和除以4/5控制信号输出多米诺骨牌的控制信号。

公开(公告)号：US08723609B2

公开(公告)日：2014-05-13

申请号：US13558360

申请日：2012-07-26

申请人： Chih-Hsiang Chang ,  Nai-Chen Cheng ,  Yu Lee ,  Ching-Yuan Yang

发明人： Chih-Hsiang Chang ,  Nai-Chen Cheng ,  Yu Lee ,  Ching-Yuan Yang

IPC分类号： H03B5/12 ,  H03B19/14 ,  H03B27/00 ,  H03C3/22 ,  H03L7/24

CPC分类号： H03B5/1212 ,  H03B5/1228 ,  H03B5/124 ,  H03B5/1243 ,  H03B5/1296 ,  H03B19/14 ,  H03B27/00 ,  H03B2200/004 ,  H03B2200/0078 ,  H03B2201/0208 ,  H03L7/24

摘要： A voltage-controlled oscillator (VCO) module including a first VCO unit, a second VCO unit, and a matching circuit is provided. The first VCO unit includes a first terminal and a second terminal and generates a first oscillator signal. The second VCO unit is coupled to the first VCO unit and generates a second oscillator signal. The matching circuit is coupled between the first VCO unit and second VCO unit. The matching circuit includes a plurality of inductor modules respectively coupled between the first terminal of the first VCO unit and the second VCO unit, between the first terminal and the second terminal of the first VCO unit, and between the second terminal of the first VCO unit and the second VCO unit. Furthermore, a method for generating oscillator signals is also provided.

摘要翻译： 提供了包括第一VCO单元，第二VCO单元和匹配电路的压控振荡器（VCO）模块。 第一VCO单元包括第一端子和第二端子，并产生第一振荡器信号。 第二VCO单元耦合到第一VCO单元并产生第二振荡器信号。 匹配电路耦合在第一VCO单元和第二VCO单元之间。 匹配电路包括分别耦合在第一VCO单元的第一端和第二VCO单元之间的多个电感器模块，位于第一VCO单元的第一端子和第二端子之间，并且在第一VCO单元的第二端子之间 和第二个VCO单元。 此外，还提供了一种用于产生振荡器信号的方法。

公开(公告)号：US20120146693A1

公开(公告)日：2012-06-14

申请号：US13114030

申请日：2011-05-23

申请人： Yu Lee ,  Nai-Chen Cheng ,  Ji-Jan Chen ,  Yuan-Hua Chu ,  Ching-Yuan Yang

发明人： Yu Lee ,  Nai-Chen Cheng ,  Ji-Jan Chen ,  Yuan-Hua Chu ,  Ching-Yuan Yang

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  G06F1/10 ,  G06F1/12 ,  H03L7/07 ,  H03L7/0812 ,  H04L7/0008

摘要： An apparatus for clock skew compensation is provided. The apparatus includes a first delay locked loop (DLL) module disposed in a first die and a second DLL module disposed in a second die. A first input terminal of the first DLL module receives a reference clock. A first input terminal of the second DLL module is electrically connected to an output terminal of the first DLL module. An output terminal of the second DLL module is electrically connected to a second input terminal of the first DLL module.

摘要翻译： 提供了一种用于时钟偏移补偿的装置。 该装置包括设置在第一管芯中的第一延迟锁定环（DLL）模块和设置在第二管芯中的第二DLL模块。 第一DLL模块的第一输入端接收参考时钟。 第二DLL模块的第一输入端电连接到第一DLL模块的输出端。 第二DLL模块的输出端电连接到第一DLL模块的第二输入端。

公开(公告)号：US08258827B2

公开(公告)日：2012-09-04

申请号：US12789424

申请日：2010-05-27

申请人： Chih-Hsiang Chang ,  Jung-Mao Lin ,  Ching-Yuan Yang

发明人： Chih-Hsiang Chang ,  Jung-Mao Lin ,  Ching-Yuan Yang

IPC分类号： H03B19/00

CPC分类号： H03B19/14

摘要： A frequency doubler receiving an in-phase oscillating signal and an inverse oscillating signal and generating an output signal oscillating at a multiplied frequency, accordingly. The frequency doubler has a first transistor, a second transistor, a first inductor and a second inductor. A first terminal of the first transistor and a first terminal of the second transistor are at a common voltage. The frequency doubler receives the in-phase oscillating signal and the inverse oscillating signal via control terminals of the first and second transistors. The first and second inductors couple a second terminal of the first transistor and a second terminal of the second transistor to an output terminal of the frequency doubler, respectively. The first and second inductors may be separate inductance devices or, in another case, be implemented by a symmetric inductor.

摘要翻译： 接收同相振荡信号的倍频器和反相振荡信号，并相应地产生以倍频振荡的输出信号。 倍频器具有第一晶体管，第二晶体管，第一电感器和第二电感器。 第一晶体管的第一端子和第二晶体管的第一端子处于公共电压。 倍频器通过第一和第二晶体管的控制端接收同相振荡信号和反相振荡信号。 第一和第二电感分别将第一晶体管的第二端子和第二晶体管的第二端子耦合到倍频器的输出端子。 第一和第二电感器可以是分离的电感器件，或者在另一种情况下可由对称电感器来实现。