摘要:
A switching device includes an input stage switch group 1-1 including a plurality of input lines, an output stage switch group 1-3 including a plurality of output lines, an intermediate stage switch group 1-2 arranged between the input stage switch group and the output stage switch group, and a scheduler 1-22 deciding a signal path of each of intermediate stage switches 1-21 in the intermediate stage switch group based on information input to the respective input lines. The intermediate stage switch group is divided into a plurality of groups, a plurality of the schedulers is arranged in a distributed fashion to correspond to the plurality of groups, respectively and the schedulers operate independently of one another.
摘要:
A switching device includes an input stage switch group 1-1 including a plurality of input lines, an output stage switch group 1-3 including a plurality of output lines, an intermediate stage switch group 1-2 arranged between the input stage switch group and the output stage switch group, and a scheduler 1-22 deciding a signal path of each of intermediate stage switches 1-21 in the intermediate stage switch group based on information input to the respective input lines. The intermediate stage switch group is divided into a plurality of groups, a plurality of the schedulers is arranged in a distributed fashion to correspond to the plurality of groups, respectively and the schedulers operate independently of one another.
摘要:
A packet error detecting device for detecting the existence of an error of the packet data transferred by a packet switching in a DMA transfer, comprising an operation unit formed by hardware for executing a necessary operation to detect a packet error in the packet data received in every block, a DMA controller for DMA transferring data from a memory storing the received data to the operation unit, previous to the DMA transfer of the data toward an external device, and a CPU for performing an error procedure if detecting a packet error as the result of the error detection by the operation unit.
摘要:
Disclosed is an ATM switch which comprises: an ATM switch unit; a switch control unit for controlling the ATM switch unit; one or more circuit accommodation units for connecting the switch with one or more external ATM networks, respectively, and an IP routing process unit for routing IP packets in a form of ATM cells. In the ATM switch, the IP routing process unit may comprise: a cell storage unit having a plurality of memories; a distributing means for distributing the ATM cells received from the ATM switch unit to the plurality of memories while grouping the ATM cells into each of the plurality of memories in accordance with an IP packet to which each of the ATM cells belongs; sending means for sending all the ATM cells belonging to an identical IP packet when the all the ATM cells belonging to the identical IP packet have been stored in respective one of the plurality of memories; and means for converting VPI/VCI (Virtual Path Identifier/ Virtual Channel Identifier) of the all the ATM cells belonging to the identical IP packet.
摘要:
A packet processing method for exchanging packet data through a plurality of layers is disclosed, that comprises the steps of storing the entire packet to a packet memory; and storing part of each packet of the packet data used in processes of a layer 2 processing portion and a layer 3 processing portion of the plurality of layers to a multi-port shared memory, the layer 2 processing portion and the layer 3 processing portion accessing the same memory space of the multi-port shared memory. In addition, a pipeline processing system is used so that when the layer 2 processing portion and the layer 3 processing portion access the shared memory, they do not interfere with each other.
摘要:
A packet processing method for exchanging packet data through a plurality of layers is disclosed, that comprises the steps of storing the entire packet to a packet memory; and storing part of each packet of the packet data used in processes of a layer 2 processing portion and a layer 3 processing portion of the plurality of layers to a multi-port shared memory, the layer 2 processing portion and the layer 3 processing portion accessing the same memory space of the multi-port shared memory. In addition, a pipeline processing system is used so that when the layer 2 processing portion and the layer 3 processing portion access the shared memory, they do not interfere with each other.
摘要:
A packet processing method for exchanging packet data through a plurality of layers is disclosed, that comprises the steps of storing the entire packet to a packet memory; and storing part of each packet of the packet data used in processes of a layer 2 processing portion and a layer 3 processing portion of the plurality of layers to a multi-port shared memory, the layer 2 processing portion and the layer 3 processing portion accessing the same memory space of the multi-port shared memory. In addition, a pipeline processing system is used so that when the layer 2 processing portion and the layer 3 processing portion access the shared memory, they do not interfere with each other.
摘要:
A table data retrieving apparatus comprises a plurality of tables in which a reference data is stored. Each table of said plurality of tables is allocated into any group of a plurality of groups. A management table stores a priority of said table. A data retrieving section selects a group based on the retrieving key by which the reference data is selected. The data retrieving section retrieves with the priority said table which is allocated into the selected group is stored.