Selective packet processing including a run-to-completion packet processing data plane

    公开(公告)号:US11811685B1

    公开(公告)日:2023-11-07

    申请号:US17813226

    申请日:2022-07-18

    CPC classification number: H04L49/3063 H04L47/56 H04L47/6255

    Abstract: An example virtual router includes a plurality of logical cores (“lcores”), where each lcore comprises a CPU core or hardware thread. The virtual router is configured to determine a latency profile, select, based at least in part on the latency profile, a packet processing mode from the plurality of packet processing modes. In response to a determination that the packet processing mode comprises the run-to-completion mode, an lcore of the plurality of lcores is configured to: read a network packet from a device queue, process the network packet to determine a destination virtual device for the network packet, the destination virtual device having a plurality of interface queues, and insert the network packet into an interface queue of the plurality of interface queues.

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