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    Methods and apparatus for transmission of groups of cells via a switch fabric
    2.
    发明授权
    Methods and apparatus for transmission of groups of cells via a switch fabric 有权
    用于通过交换结构传输小区组的方法和装置

    公开(公告)号：US09077466B2

    公开(公告)日：2015-07-07

    申请号：US13692425

    申请日：2012-12-03

    Applicant: Juniper Networks, Inc.

    Inventor： Sarin Thomas ,  Srihari Vegesna ,  Pradeep Sindhu ,  Chi-Chung Kenny Chen ,  Jean-Marc Frailong ,  David J. Ofelt ,  Philip A. Thomas ,  Chang-Hong Wu

    IPC: H04L12/28 ,  H04J3/00 ,  H04L12/947 ,  H04L12/937

    CPC classification number: H04J3/00 ,  H04L49/251 ,  H04L49/254

    Abstract: In one embodiment, a method can include receiving at an egress schedule module a request to schedule transmission of a group of cells from an ingress queue through a switch fabric of a multi-stage switch. The ingress queue can be associated with an ingress stage of the multi-stage switch. The egress schedule module can be associated with an egress stage of the multi-stage switch. The method can also include determining, in response to the request, that an egress port at the egress stage of the multi-stage switch is available to transmit the group of cells from the multi-stage switch.

    Abstract translation: 在一个实施例中，一种方法可以包括在出口调度模块处接收通过多级交换机的交换结构调度来自进入队列的小区的传输的请求。 入站队列可以与多级交换机的进入级相关联。 出口调度模块可以与多级交换机的出口级相关联。 该方法还可以包括响应于该请求确定多级交换机的出口级的出口端口可用于从多级交换机发送小区组。

    Multi-bank queuing architecture for higher bandwidth on-chip memory buffer
    3.
    发明授权
    Multi-bank queuing architecture for higher bandwidth on-chip memory buffer 失效
    用于更高带宽片上存储器缓冲器的多库排队架构

    公开(公告)号：US08713220B2

    公开(公告)日：2014-04-29

    申请号：US13732198

    申请日：2012-12-31

    Applicant: Juniper Networks, Inc.

    Inventor： Anurag Agrawal ,  Philip A. Thomas

    IPC: G06F3/00

    CPC classification number: H04L47/522 ,  H04L49/9047 ,  H04L49/9089

    Abstract: A network device includes a main storage memory and a queue handling component. The main storage memory includes multiple memory banks which store a plurality of packets for multiple output queues. The queue handling component controls write operations to the multiple memory banks and controls read operations from the multiple memory banks, where the read operations for at least one of the multiple output queues alternates sequentially between the each of the multiple memory banks, and where the read operations and the write operations occur during a same clock period on different ones of the multiple memory banks.

    Abstract translation: 网络设备包括主存储存储器和队列处理组件。 主存储器包括存储用于多个输出队列的多个分组的多个存储体。 队列处理组件控制对多个存储体的写入操作并控制来自多个存储体的读取操作，其中多个输出队列中的至少一个的读取操作在多个存储器组中的每一个之间顺序地交替，并且读取 操作和写入操作在多个存储体中的不同存储体上的同一时钟周期内发生。

    Multi-chassis topology discovery using in-band signaling
    5.
    发明授权
    Multi-chassis topology discovery using in-band signaling 有权
    使用带内信令的多机架拓扑发现

    公开(公告)号：US09258192B2

    公开(公告)日：2016-02-09

    申请号：US14146981

    申请日：2014-01-03

    Applicant: Juniper Networks, Inc.

    Inventor： Philip A. Thomas ,  Anurag Agrawal

    IPC: H04L12/28 ,  H04L12/24

    CPC classification number: H04L41/12 ,  H04L41/0876

    Abstract: A multi-chassis network device may automatically detect whether cables connected between chassis devices are correctly inserted. The device may insert, into a first data stream output from a first port of the device, control information identifying the first port. The device may receive, from a second data stream received by the first port of the device, second control information identifying a second port, at another device connected to the device via a cable. The device may determine, based on the second control information, whether the connection of the first port to the second port, via the cable, is valid and cause, when the connection of the first port to the second port is determined to not be valid, the device to output an indication that the connection is not valid or to reconfigure the device to make the connection of the first port to the second port valid.

    Abstract translation: 多机箱网络设备可以自动检测连接在机箱设备之间的电缆是否正确插入。 设备可以将从第一端口输出的第一数据流插入到识别第一端口的控制信息中。 设备可以从设备的第一端口接收的第二数据流接收标识第二端口的第二控制信息，在经由电缆连接到设备的另一设备处。 设备可以基于第二控制信息确定第一端口到第二端口的连接是否经过电缆是有效的，并且当第一端口到第二端口的连接被确定为不是有效的时 ，用于输出连接无效的指示的设备或重新配置设备以使第一端口与第二端口的连接有效。

    Rate controlled first in first out (FIFO) queues for clock domain crossing
    6.
    发明授权
    Rate controlled first in first out (FIFO) queues for clock domain crossing 有权
    速率控制先进先出（FIFO）队列用于时钟域交叉

    公开(公告)号：US09104345B2

    公开(公告)日：2015-08-11

    申请号：US14211805

    申请日：2014-03-14

    Applicant: Juniper Networks, Inc.

    Inventor： Anurag Agrawal ,  Philip A. Thomas

    IPC: G06F3/00 ,  G06F1/04 ,  G06F5/12

    CPC classification number: G06F5/12 ,  G06F1/04

    Abstract: First in, first out (FIFO) queues may be used to transfer data between a producer clock domain and a number of consumer clock domains. In one implementation, a control component for the FIFO queues may include a number of counters, corresponding to each of the consumer clock domains, each of the counters maintaining a count value relating to an amount of data read by the corresponding consumer clock domain. The control component may additionally include a credit deduction component coupled to the count values of the counters, the credit deduction component determining whether any of the count values is above a threshold, and in response to the determination that any of the count values is above the threshold, reducing the count value of each of the counters and issuing a write pulse signal to the producer clock domain, the write pulse signal causing the producer clock domain to perform a write operation to the FIFO queues.

    Abstract translation: 首先，先出（FIFO）队列可以用于在生成器时钟域和多个消费者时钟域之间传送数据。 在一个实现中，用于FIFO队列的控制组件可以包括与每个消费者时钟域相对应的多个计数器，每个计数器保持与由相应的消费者时钟域读取的数据量相关的计数值。 控制部件还可以包括耦合到计数器的计数值的信用扣除部件，信用扣除部件确定任何计数值是否高于阈值，并且响应于确定任何计数值高于 阈值，减少每个计数器的计数值并向生成器时钟域发出写入脉冲信号，该写入脉冲信号使得生成器时钟域对FIFO队列执行写入操作。

    METHODS AND APPARATUS FOR TRANSMISSION OF GROUPS OF CELLS VIA A SWITCH FABRIC
    7.
    发明申请
    METHODS AND APPARATUS FOR TRANSMISSION OF GROUPS OF CELLS VIA A SWITCH FABRIC 有权
    用于通过开关织物传输细胞群的方法和装置

    公开(公告)号：US20130121343A1

    公开(公告)日：2013-05-16

    申请号：US13692425

    申请日：2012-12-03

    Applicant: Juniper Networks, Inc.

    Inventor： Sarin Thomas ,  Srihari Vegesna ,  Pradeep Sindhu ,  Chi-Chung Kenny Chen ,  Jean-Marc Frailong ,  David J. Ofelt ,  Philip A. Thomas ,  Chang-Hong Wu

    IPC: H04J3/00

    CPC classification number: H04J3/00 ,  H04L49/251 ,  H04L49/254

    Abstract: In one embodiment, a method can include receiving at an egress schedule module a request to schedule transmission of a group of cells from an ingress queue through a switch fabric of a multi-stage switch. The ingress queue can be associated with an ingress stage of the multi-stage switch. The egress schedule module can be associated with an egress stage of the multi-stage switch. The method can also include determining, in response to the request, that an egress port at the egress stage of the multi-stage switch is available to transmit the group of cells from the multi-stage switch.

    Abstract translation: 在一个实施例中，一种方法可以包括在出口调度模块处接收通过多级交换机的交换结构调度来自进入队列的小区的传输的请求。 入站队列可以与多级交换机的进入级相关联。 出口调度模块可以与多级交换机的出口级相关联。 该方法还可以包括响应于该请求确定多级交换机的出口级的出口端口可用于从多级交换机发送该小区组。

    Methods and apparatus for randomly distributing traffic in a multi-path switch fabric
    8.
    发明授权
    Methods and apparatus for randomly distributing traffic in a multi-path switch fabric 有权

    公开(公告)号：US10097479B1

    公开(公告)日：2018-10-09

    申请号：US15087642

    申请日：2016-03-31

    Applicant: Juniper Networks, Inc.

    Inventor： Philip A. Thomas ,  Sarin Thomas ,  Jean-Marc Frailong ,  Pradeep Sindhu

    IPC: H04L12/947 ,  H04L12/707 ,  H04L12/935

    Abstract: In some embodiments, an apparatus comprises a schedule module within a switch fabric system. At a first time, the schedule module is configured to access a list of status indicators associated with a group of egress port indicators. The list of status indicators includes a set of status indicators each of which has a value greater than a threshold. The schedule module is configured to randomly select a status indicator from the set of status indicators and configured to reduce the value of the selected status indicator. The schedule module is then configured to send the egress port indicator associated with the selected status indicator such that a data cell is sent from an egress port associated with that egress port indicator. At a second time, when the value of every status indicator from the list of status indicators is not greater than the threshold, the schedule module is configured to increase the value of every status indicator above the threshold.

    Fast chromatic dispersion estimation
    9.
    发明授权
    Fast chromatic dispersion estimation 有权
    快速色散估计

    公开(公告)号：US09225431B1

    公开(公告)日：2015-12-29

    申请号：US13854023

    申请日：2013-03-29

    Applicant: Juniper Networks, Inc.

    Inventor： Murat Arabaci ,  Christian Malouin ,  Philip A. Thomas ,  Theodore John Schmidt ,  Roberto Marcoccia

    IPC: H04B10/06 ,  H04B10/61

    CPC classification number: H04B10/6161 ,  H04B10/25133

    Abstract: This disclosure describes the Fast Chromatic Dispersion Estimation (FCDE) techniques which corrects for chromatic dispersion in high data rate optical communications systems such as some coherent optical communications systems. FCDE may utilize transform such as fast-Fourier transforms to estimate the chromatic dispersion. From an estimate of the chromatic dispersion, the techniques may determine filter tap coefficients for compensating the chromatic dispersion.

    Abstract translation: 本公开描述了在诸如一些相干光通信系统的高数据速率光通信系统中校正色散的快速色散估计（FCDE）技术。 FCDE可以利用诸如快速傅里叶变换的变换来估计色散。 根据色散的估计，这些技术可以确定用于补偿色散的滤波器抽头系数。

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