Systems and methods for performing parallel digital phase-locked-loop
    1.
    发明授权
    Systems and methods for performing parallel digital phase-locked-loop 有权
    用于执行并行数字锁相环的系统和方法

    公开(公告)号:US08379788B2

    公开(公告)日:2013-02-19

    申请号:US12818158

    申请日:2010-06-18

    IPC分类号: H03D3/24

    CPC分类号: H03L7/07 H04L2027/0067

    摘要: A parallel phase locked loop (PLL) system includes a first chain of a plurality of pre-locking PLLs that operates from a free-run state to a locked state; and a second chain of a plurality of PLLs to work from the locked-state to recover signal output.

    摘要翻译: 并行锁相环(PLL)系统包括从自由运行状态到锁定状态操作的多个预锁定PLL的第一链; 以及多个PLL的第二链,其从锁定状态工作以恢复信号输出。

    SYSTEMS AND METHODS FOR PERFORMING DYNAMIC CHANNEL ESTIMATION
    2.
    发明申请
    SYSTEMS AND METHODS FOR PERFORMING DYNAMIC CHANNEL ESTIMATION 有权
    用于执行动态通道估计的系统和方法

    公开(公告)号:US20120099637A1

    公开(公告)日:2012-04-26

    申请号:US12911455

    申请日:2010-10-25

    IPC分类号: H04L27/01 H03D1/00

    摘要: Systems and methods are disclosed for dynamic channel estimation in a digital receiver by performing a dynamic equalization on an incoming signal to compensate for channel distortion; independently estimating one or more channel parameters for the dynamic equalization, wherein the one or more channel parameters track channel change; determining a convolution of the channel parameters and updating the parameters for the dynamic equalization for subsequent processing of incoming signal; and providing an equalized output from the digital receiver.

    摘要翻译: 公开了在数字接收机中通过对输入信号执行动态均衡以补偿信道失真的系统和方法来进行动态信道估计; 独立地估计所述动态均衡的一个或多个信道参数,其中所述一个或多个信道参数跟踪信道改变; 确定信道参数的卷积并更新用于动态均衡的参数以用于后续处理输入信号; 并提供来自数字接收机的均衡输出。

    HITLESS PROTECTION FOR TRANSMITTING TRAFFIC IN HIGH-SPEED SWITCHING SYSTEM
    3.
    发明申请
    HITLESS PROTECTION FOR TRANSMITTING TRAFFIC IN HIGH-SPEED SWITCHING SYSTEM 审中-公开
    在高速切换系统中传输交通的无害保护

    公开(公告)号:US20130084062A1

    公开(公告)日:2013-04-04

    申请号:US13543541

    申请日:2012-07-06

    IPC分类号: H04L12/24 H04B10/08

    CPC分类号: H04L49/10

    摘要: A system to provide hitless protection includes a primary line card with a synchronous interface, the primary line card processing traffic with cells and encapsulating the traffic into synchronous frames in a predetermined format; and a back-up line card with a synchronous interface, the back-up line card processing the traffic with the cells and encapsulating the traffic into the synchronous frames in the predetermined format, wherein each line card includes a buffer to align the traffic before transmission, wherein the cell information sent by the primary line card is passed to the back-up line card, and wherein the back-up line card follows the received information to send to the destination cell.

    摘要翻译: 提供无中断保护的系统包括具有同步接口的主线卡,主线卡处理具有小区的业务,并以预定格式将业务封装成同步帧; 以及具有同步接口的备用线路卡,所述备用线路卡处理与所述小区的业务并且以预定格式将业务封装到所述同步帧中,其中每个线路卡包括用于在传输之前对准业务的缓冲器 其中由主线路卡发送的小区信息被传递到备用线路卡,并且其中备用线路卡遵循所接收的信息以发送到目的地小区。

    Systems and methods for performing dynamic channel estimation
    4.
    发明授权
    Systems and methods for performing dynamic channel estimation 有权
    用于执行动态信道估计的系统和方法

    公开(公告)号:US08379785B2

    公开(公告)日:2013-02-19

    申请号:US12911455

    申请日:2010-10-25

    IPC分类号: H04L7/00 H04B1/10 H04N5/00

    摘要: Systems and methods are disclosed for dynamic channel estimation in a digital receiver by performing a dynamic equalization on an incoming signal to compensate for channel distortion; independently estimating one or more channel parameters for the dynamic equalization, wherein the one or more channel parameters track channel change; determining a convolution of the channel parameters and updating the parameters for the dynamic equalization for subsequent processing of incoming signal; and providing an equalized output from the digital receiver.

    摘要翻译: 公开了在数字接收机中通过对输入信号执行动态均衡以补偿信道失真的系统和方法来进行动态信道估计; 独立地估计所述动态均衡的一个或多个信道参数,其中所述一个或多个信道参数跟踪信道改变; 确定信道参数的卷积并更新用于动态均衡的参数以用于后续处理输入信号; 并提供来自数字接收机的均衡输出。

    Method for source synchronous high-speed signal synchronization
    5.
    发明授权
    Method for source synchronous high-speed signal synchronization 有权
    源同步高速信号同步方法

    公开(公告)号:US08358726B2

    公开(公告)日:2013-01-22

    申请号:US12814371

    申请日:2010-06-11

    IPC分类号: H04L7/00

    CPC分类号: H03L7/0814

    摘要: A source synchronous signal synchronization system includes a differential signal receiver; a tunable input delay element coupled to the receiver; an input serializer/deserializer (ISerDes) coupled to the tunable input delay; an alignment unit coupled to the ISerDes; and a delay control unit coupled to the tunable input delay, the ISerDes, and the alignment unit.

    摘要翻译: 源同步信号同步系统包括差分信号接收机; 耦合到所述接收器的可调输入延迟元件; 耦合到可调输入延迟的输入串行器/解串器(ISerDes); 耦合到ISerDes的对准单元; 以及与可调输入延迟耦合的延迟控制单元,ISerDes和对准单元。

    RING-BASED HIGH SPEED BUS INTERFACE
    6.
    发明申请
    RING-BASED HIGH SPEED BUS INTERFACE 审中-公开
    基于环的高速总线接口

    公开(公告)号:US20100122003A1

    公开(公告)日:2010-05-13

    申请号:US12549515

    申请日:2009-08-28

    IPC分类号: G06F13/00

    摘要: A communication system management interface includes a control master; and one or more slaves under management by the control master; wherein each device, either the control master or slave, has at least an input signal connected to an output signal of another device to form a daisy-chain.

    摘要翻译: 通信系统管理接口包括控制主机; 以及由控制主管理的一个或多个奴隶; 其中每个设备(控制主机或从机)至少具有连接到另一设备的输出信号的输入信号以形成菊花链。

    Systems and methods for blind equalization in a digital receiver
    7.
    发明授权
    Systems and methods for blind equalization in a digital receiver 有权
    数字接收机盲均衡的系统和方法

    公开(公告)号:US08488652B2

    公开(公告)日:2013-07-16

    申请号:US12911416

    申请日:2010-10-25

    IPC分类号: H04B1/00 H03F3/45

    摘要: A digital receiver system to recover signals from inter-symbol-interference includes a finite impulse response (FIR) filter using convolution to recover signals; and a channel estimator coupled to the FIR filter to estimate FIR coefficients, wherein the channel estimator uses a second order expectation and a fourth order expectation from a convolution to calculate error function.

    摘要翻译: 用于从符号间干扰恢复信号的数字接收机系统包括使用卷积恢复信号的有限脉冲响应(FIR)滤波器; 以及耦合到FIR滤波器以估计FIR系数的信道估计器,其中信道估计器使用来自卷积的二阶期望和四阶期望来计算误差函数。

    SYSTEMS AND METHODS FOR BLIND EQUALIZATION IN A DIGITAL RECEIVER
    8.
    发明申请
    SYSTEMS AND METHODS FOR BLIND EQUALIZATION IN A DIGITAL RECEIVER 有权
    数字接收机中盲均衡的系统和方法

    公开(公告)号:US20110261867A1

    公开(公告)日:2011-10-27

    申请号:US12911416

    申请日:2010-10-25

    IPC分类号: H04B17/00

    摘要: A digital receiver system to recover signals from inter-symbol-interference includes a finite impulse response (FIR) filter using convolution to recover signals; and a channel estimator coupled to the FIR filter to estimate FIR coefficients, wherein the channel estimator uses a second order expectation and a fourth order expectation from a convolution to calculate error function.

    摘要翻译: 用于从符号间干扰恢复信号的数字接收机系统包括使用卷积恢复信号的有限脉冲响应(FIR)滤波器; 以及耦合到FIR滤波器以估计FIR系数的信道估计器,其中信道估计器使用来自卷积的二阶期望和四阶期望来计算误差函数。