公开(公告)号：US20130038583A1

公开(公告)日：2013-02-14

申请号：US13642894

申请日：2011-01-28

申请人： Junya Shimada ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Chikao Yamasaki ,  Masahiro Yoshida ,  Satoshi Horiuchi ,  Isao Ogasawara

发明人： Junya Shimada ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Chikao Yamasaki ,  Masahiro Yoshida ,  Satoshi Horiuchi ,  Isao Ogasawara

IPC分类号： G11C19/00 ,  G06F3/038 ,  G09G3/36

CPC分类号： G11C19/28 ,  G09G3/3677

摘要： Provided is a shift register circuit which includes: first through N-th circuit sections (1a, 1b) (N is an integer equal to or larger than 2) in each of which a plurality of shift register stages (SR1, SR2, . . . , SRn) are connected in cascade; and supply wires (10b, 10c, 10e, 10f). Each of the first through N-th circuit sections (1a, 1b) receives drive signals (CKA1, CKA2, CKB1, CKB2) for driving the shift register stages (SR1, SR2, . . . , SRn) via supply wires (10b, 10c, 10e, 10f) exclusive for the each of the first through N-th circuit sections (1a, 1b).

摘要翻译： 提供一种移位寄存器电路，其包括：第一至第N电路部分（1a，1b）（N是等于或大于2的整数），其中每个电路部分中的多个移位寄存器级（SR1，SR2，...， 。，SRn）级联连接; 和电源线（10b，10c，10e，10f）。 第一至第N电路部分（1a，1b）中的每一个接收用于驱动移位寄存器级（SR1，SR2，...，SRn）的驱动信号（CKA1，CKA2，CKB1，CKB2） 10c，10e，10f）分别用于第一至第N电路部分（1a，1b）。

公开(公告)号：US20140306225A1

公开(公告)日：2014-10-16

申请号：US13809930

申请日：2011-05-20

申请人： Tetsuo Kikuchi ,  Yoshiharu Kataoka ,  Shinya Tanaka ,  Junya Shimada ,  Chikao Yamasaki

发明人： Tetsuo Kikuchi ,  Yoshiharu Kataoka ,  Shinya Tanaka ,  Junya Shimada ,  Chikao Yamasaki

IPC分类号： H01L29/786 ,  H01L27/12

CPC分类号： H01L29/78696 ,  H01L27/0207 ,  H01L27/12 ,  H01L27/1222 ,  H01L27/1225 ,  H01L29/7869

摘要： Thin film transistors having a high current drive capability and a suitable threshold voltage are provided. The thin film transistor includes a gate electrode, an insulating layer formed on the gate electrode, a semiconductor layer formed on the insulating layer, and source/drain electrodes formed on the semiconductor layer. The semiconductor layer includes a plurality of regions separated from each other in a longitudinal direction of the source/drain electrodes.

摘要翻译： 提供具有高电流驱动能力和合适阈值电压的薄膜晶体管。 薄膜晶体管包括栅电极，形成在栅电极上的绝缘层，形成在绝缘层上的半导体层以及形成在半导体层上的源/漏电极。 半导体层包括在源极/漏极的纵向彼此分离的多个区域。

公开(公告)号：US08586987B2

公开(公告)日：2013-11-19

申请号：US13394621

申请日：2010-05-21

申请人： Tetsuo Kikuchi ,  Shinya Tanaka ,  Junya Shimada ,  Chikao Yamasaki

发明人： Tetsuo Kikuchi ,  Shinya Tanaka ,  Junya Shimada ,  Chikao Yamasaki

IPC分类号： H01L29/04 ,  H01L29/15 ,  G02F1/1343 ,  H01L21/84

CPC分类号： H01L27/3276 ,  G02F1/133553 ,  G02F1/13452 ,  G02F1/13454 ,  G02F1/13458 ,  G02F2001/13629 ,  H01L27/124

摘要： A second stem wires (17c), formed by a reflective pixel electrode layer formed as a different layer from first stem wires (17a), is provided in such a way as to extend along a long side of its adjacent one of the first stem wires (17a). This makes it possible to achieve a TFT array substrate (1) on which a gate drive circuit (15) and its wires (17a, 17b, 17c, 18) have been monolithically formed, wherein the width of a frame part in which the a gate drive circuit (15) and its wires (17a, 17b, 17c, 18) are formed can be reduced.

摘要翻译： 由与第一杆线（17a）形成为不同层的反射像素电极层形成的第二杆线（17c）设置成沿其相邻的第一杆线的长边延伸 （17a）。 这使得可以实现其栅极驱动电路（15）及其导线（17a，17b，17c，18）已经被整体地形成在其上的框架部分的宽度，其中a 栅极驱动电路（15）及其导线（17a，17b，17c，18）可以被形成。

公开(公告)号：US20120218237A1

公开(公告)日：2012-08-30

申请号：US13504133

申请日：2010-06-02

申请人： Junya Shimada ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Chikao Yamasaki

发明人： Junya Shimada ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Chikao Yamasaki

IPC分类号： G09G5/00

CPC分类号： G02F1/13452 ,  G02F1/13454

摘要： The present invention is to provide a display panel and a display apparatus which can reduce the picture-frame area while sufficiently preventing the delay of signals by allowing a required amount of current to flow. The display panel of the present invention is a display panel which includes a circuit substrate, and an opposed substrate facing the circuit substrate, and which is featured in that the circuit section is arranged in the picture-frame area of the display panel, in that the circuit section includes trunk wiring, and branch wiring connected to the gate electrode or the source electrode of a transistor in the circuit section, and in that all or a part of the trunk wiring is provided on the opposed substrate, and the branch wiring is provided on the circuit substrate so as to be electrically connected to the trunk wiring via a conductor.

摘要翻译： 本发明提供一种显示面板和显示装置，其能够通过允许所需量的电流流动来充分防止信号的延迟，从而减小画面区域。 本发明的显示面板是包括电路基板和面对电路基板的相对基板的显示面板，其特征在于，电路部分布置在显示面板的图像框区域中，其中 电路部分包括主干布线和连接到电路部分中的晶体管的栅电极或源电极的分支布线，并且所述干线布线的全部或一部分设置在相对的基板上，分支布线为 设置在电路基板上，以经由导体与主干布线电连接。

公开(公告)号：US08786582B2

公开(公告)日：2014-07-22

申请号：US13504133

申请日：2010-06-02

申请人： Junya Shimada ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Chikao Yamasaki

发明人： Junya Shimada ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Chikao Yamasaki

IPC分类号： G09G5/00 ,  G02F1/1345

CPC分类号： G02F1/13452 ,  G02F1/13454

摘要： The present invention is to provide a display panel and a display apparatus which can reduce the picture-frame area while sufficiently preventing the delay of signals by allowing a required amount of current to flow. The display panel of the present invention is a display panel which includes a circuit substrate, and an opposed substrate facing the circuit substrate, and which is featured in that the circuit section is arranged in the picture-frame area of the display panel, in that the circuit section includes trunk wiring, and branch wiring connected to the gate electrode or the source electrode of a transistor in the circuit section, and in that all or a part of the trunk wiring is provided on the opposed substrate, and the branch wiring is provided on the circuit substrate so as to be electrically connected to the trunk wiring via a conductor.

摘要翻译： 本发明提供一种显示面板和显示装置，其能够通过允许所需量的电流流动来充分防止信号的延迟，从而减小画面区域。 本发明的显示面板是包括电路基板和面对电路基板的相对基板的显示面板，其特征在于，电路部分布置在显示面板的图像框区域中，其中 电路部分包括主干布线和连接到电路部分中的晶体管的栅电极或源电极的分支布线，并且所述干线布线的全部或一部分设置在相对的基板上，分支布线为 设置在电路基板上，以经由导体与主干布线电连接。

公开(公告)号：US20130028370A1

公开(公告)日：2013-01-31

申请号：US13637367

申请日：2011-01-06

申请人： Tetsuo Kikuchi ,  Shinya Tanaka ,  Junya Shimada ,  Chikao Yamasaki

发明人： Tetsuo Kikuchi ,  Shinya Tanaka ,  Junya Shimada ,  Chikao Yamasaki

IPC分类号： G11C19/28

CPC分类号： G11C19/184 ,  G09G3/3677 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/28

摘要： A shift register is formed by connecting unit circuits 11 in multi-stage. One electrode of a capacitor Cap2 in the unit circuit 11 is connected to the gate terminal (node N1) of a transistor T2, and the other connected to a node N2. A compensation circuit composed of transistors T3 to T5 provides a clock signal CKB to the node N2 when the node N1 potential is at low level, and applies a low-level potential to the node N2 when the node N1 potential is at high level. Accordingly, even when the gate potential of the transistor T2 changes with a change in a clock signal CK, a signal that cancels out the change is provided through the capacitor Cap2, stabilizing the gate potential of the transistor T2. Thus, a change in the control terminal potential of an output transistor associated with a change in a clock signal is prevented.

摘要翻译： 通过多级连接单元电路11形成移位寄存器。 单元电路11中的电容器Cap2的一个电极连接到晶体管T2的栅极端子（节点N1），另一个连接到节点N2。 当晶体管T3至T5组成的补偿电路在节点N1电位处于低电平时向节点N2提供时钟信号CKB，并且当节点N1电位处于高电平时向节点N2施加低电平电位。 因此，即使当晶体管T2的栅极电位随着时钟信号CK的变化而变化时，通过电容器Cap2提供抵消变化的信号，从而稳定晶体管T2的栅极电位。 因此，防止与时钟信号的变化相关联的输出晶体管的控制端电位的变化。

公开(公告)号：US09029861B2

公开(公告)日：2015-05-12

申请号：US13809930

申请日：2011-05-20

申请人： Tetsuo Kikuchi ,  Yoshiharu Kataoka ,  Shinya Tanaka ,  Junya Shimada ,  Chikao Yamasaki

发明人： Tetsuo Kikuchi ,  Yoshiharu Kataoka ,  Shinya Tanaka ,  Junya Shimada ,  Chikao Yamasaki

IPC分类号： H01L29/10 ,  H01L29/76 ,  H01L31/036 ,  H01L31/112 ,  H01L29/786 ,  H01L27/12 ,  H01L27/02

CPC分类号： H01L29/78696 ,  H01L27/0207 ,  H01L27/12 ,  H01L27/1222 ,  H01L27/1225 ,  H01L29/7869

摘要： Thin film transistors having a high current drive capability and a suitable threshold voltage are provided. The thin film transistor includes a gate electrode, an insulating layer formed on the gate electrode, a semiconductor layer formed on the insulating layer, and source/drain electrodes formed on the semiconductor layer. The semiconductor layer includes a plurality of regions separated from each other in a longitudinal direction of the source/drain electrodes.

摘要翻译： 提供具有高电流驱动能力和合适阈值电压的薄膜晶体管。 薄膜晶体管包括栅电极，形成在栅电极上的绝缘层，形成在绝缘层上的半导体层以及形成在半导体层上的源/漏电极。 半导体层包括在源极/漏极的纵向彼此分离的多个区域。

公开(公告)号：US08781059B2

公开(公告)日：2014-07-15

申请号：US13637367

申请日：2011-01-06

申请人： Tetsuo Kikuchi ,  Shinya Tanaka ,  Junya Shimada ,  Chikao Yamasaki

发明人： Tetsuo Kikuchi ,  Shinya Tanaka ,  Junya Shimada ,  Chikao Yamasaki

IPC分类号： G11C19/00

CPC分类号： G11C19/184 ,  G09G3/3677 ,  G09G2310/0267 ,  G09G2310/0286 ,  G11C19/28

摘要： A shift register is formed by connecting unit circuits 11 in multi-stage. One electrode of a capacitor Cap2 in the unit circuit 11 is connected to the gate terminal (node N1) of a transistor T2, and the other connected to a node N2. A compensation circuit composed of transistors T3 to T5 provides a clock signal CKB to the node N2 when the node N1 potential is at low level, and applies a low-level potential to the node N2 when the node N1 potential is at high level. Accordingly, even when the gate potential of the transistor T2 changes with a change in a clock signal CK, a signal that cancels out the change is provided through the capacitor Cap2, stabilizing the gate potential of the transistor T2. Thus, a change in the control terminal potential of an output transistor associated with a change in a clock signal is prevented.

摘要翻译： 通过多级连接单元电路11形成移位寄存器。 单元电路11中的电容器Cap2的一个电极连接到晶体管T2的栅极端子（节点N1），另一个连接到节点N2。 当晶体管T3至T5组成的补偿电路在节点N1电位处于低电平时向节点N2提供时钟信号CKB，并且当节点N1电位处于高电平时向节点N2施加低电平电位。 因此，即使当晶体管T2的栅极电位随着时钟信号CK的变化而变化时，通过电容器Cap2提供抵消变化的信号，从而稳定晶体管T2的栅极电位。 因此，防止与时钟信号的变化相关联的输出晶体管的控制端电位的变化。

公开(公告)号：US08742424B2

公开(公告)日：2014-06-03

申请号：US13511661

申请日：2010-07-09

申请人： Chikao Yamasaki ,  Tetsuo Kikuchi ,  Shinya Tanaka ,  Junya Shimada

发明人： Chikao Yamasaki ,  Tetsuo Kikuchi ,  Shinya Tanaka ,  Junya Shimada

IPC分类号： H01L29/04

CPC分类号： H01L27/124 ,  G09G3/3266 ,  G09G3/3677 ,  G09G2300/0408 ,  G09G2310/0286 ,  G11C19/184 ,  G11C19/28 ,  H01L29/41733 ,  H01L29/42384

摘要： The present invention provides a shift register and a display device, each of which operates stably. The present invention relate to a shift register, comprising a thin-film transistor which includes a source electrode, a drain electrode, and a gate electrode, the thin-film transistor being a bottom gate thin-film transistor which includes a comb-shaped source/drain structure, the gate electrode being provided with at least one of a cut and an opening in at least one of a region overlapping with the source electrode and a region overlapping with the drain electrode.

摘要翻译： 本发明提供了一种移位寄存器和显示装置，每个都能稳定地工作。 本发明涉及一种移位寄存器，包括一个薄膜晶体管，它包括一个源电极，一个漏电极和一个栅电极，该薄膜晶体管是一个底栅薄膜晶体管，它包括一个梳形源 漏极结构，栅电极在与源电极重叠的区域和与漏电极重叠的区域中的至少一个区域中设置有切割开口和开口中的至少一个。

公开(公告)号：US08575620B2

公开(公告)日：2013-11-05

申请号：US13697148

申请日：2011-01-25

申请人： Chikao Yamasaki ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Junya Shimada

发明人： Chikao Yamasaki ,  Shinya Tanaka ,  Tetsuo Kikuchi ,  Junya Shimada

IPC分类号： H01L27/14

CPC分类号： H05K1/18 ,  G02F1/13454 ,  H01L27/1225 ,  H01L27/1251 ,  H05K7/00

摘要： The present invention provides a circuit board with a reduced circuit area, and a display device comprising the circuit board and a narrower picture frame. The circuit board of the present invention comprises: a bottom gate thin film transistor comprising a first semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode; and a top gate thin film transistor comprising a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode, wherein the first semiconductor layer and the second semiconductor layer are formed from the same material, and the first drain electrode or the first source electrode and the second gate electrode are connected without interposing any other thin film transistor therebetween, and have the same electric potential.

摘要翻译： 本发明提供一种具有减小电路面积的电路板，以及包括电路板和较窄图像帧的显示装置。 本发明的电路板包括：底栅薄膜晶体管，包括第一半导体层，第一栅电极，第一源电极和第一漏电极; 以及包括第二半导体层，第二栅电极，第二源电极和第二漏电极的顶栅薄膜晶体管，其中所述第一半导体层和所述第二半导体层由相同的材料形成，并且所述第一漏极 电极或第一源电极和第二栅极电极连接而不在其间插入任何其它薄膜晶体管，并且具有相同的电位。