Scoreboard cache coherence in a graphics pipeline
    1.
    发明授权
    Scoreboard cache coherence in a graphics pipeline 有权
    记分板缓存在图形管道中的一致性

    公开(公告)号:US09183607B1

    公开(公告)日:2015-11-10

    申请号:US11893431

    申请日:2007-08-15

    CPC分类号: G06T15/005 G06T1/60 G06T11/40

    摘要: A method in system for latency buffered scoreboarding in a graphics pipeline of a graphics processor. The method includes receiving a graphics primitive for rasterization in a raster stage of a graphics processor and rasterizing the graphics primitive to generate a plurality pixels related to the graphics primitive. An ID stored to account for an initiation of parameter evaluation for each of the plurality of pixels as the pixels are transmitted to a subsequent stage of the graphics processor. A buffer is used to store the fragment data resulting from the parameter evaluation for each of the plurality of pixels by the subsequent stage. The ID and the fragment data from the buffering are compared to determine whether they correspond to one another. The completion of parameter evaluation for each of the plurality of pixels is accounted for when the ID and the fragment data match and as the fragment data is written to a memory.

    摘要翻译: 一种用于在图形处理器的图形管线中等待时间缓冲记分板的系统中的方法。 该方法包括在图形处理器的光栅级中接收用于光栅化的图形基元,并且对图形基元进行光栅化以生成与图形基元相关的多个像素。 存储的ID用于当像素被传送到图形处理器的后续阶段时考虑对于多个像素中的每一个的参数评估的启动。 缓冲器用于存储由后续阶段的多个像素中的每一个的参数评估产生的片段数据。 比较来自缓冲的ID和片段数据以确定它们是否彼此对应。 当ID和片段数据匹配并且片段数据被写入存储器时,对多个像素中的每一个的参数评估的完成进行了说明。