公开(公告)号：US08339190B2

公开(公告)日：2012-12-25

申请号：US13012881

申请日：2011-01-25

申请人： Kazuo Otsuga ,  Yusuke Kanno ,  Yoshio Takazawa

发明人： Kazuo Otsuga ,  Yusuke Kanno ,  Yoshio Takazawa

IPC分类号： G05F1/10

CPC分类号： G01R31/31725 ,  G01R31/3004 ,  H01L2924/0002 ,  H01L2924/00

摘要： AVS (Adaptive Voltage Scaling) technique, by which variability and uncertainty are both taken into account. In the system arranged for AVS technique, a detection circuit optimum for each type of process variation is set. Examples of the detection circuit so arranged include a first measurement circuit for detection of variability, which produces a relative value with respect to the gate delay mean value, and a second measurement circuit for detection of uncertainty, which produces a relative value related to the gate delay standard deviation. The first and second measurement circuits are provided separately from each other. The control information for deciding the supply voltage is prepared based on relative values produced by the detection circuits. When preparing the control information, reference is made to e.g. a table data.

摘要翻译： AVS（自适应电压调节）技术，其中考虑了变异性和不确定性。 在安排AVS技术的系统中，设置对于每种类型的处理变化最佳的检测电路。 如此布置的检测电路的示例包括用于检测相对于门延迟平均值的相对值的可变性的第一测量电路和用于检测不确定性的第二测量电路，其产生与门相关的相对值 延迟标准偏差。 第一和第二测量电路彼此分开设置。 用于决定电源电压的控制信息是根据检测电路产生的相对值来准备的。 在准备控制信息时， 一个表数据。

公开(公告)号：US20110181337A1

公开(公告)日：2011-07-28

申请号：US13012881

申请日：2011-01-25

申请人： KAZUO OTSUGA ,  Yusuke Kanno ,  Yoshio Takazawa

发明人： KAZUO OTSUGA ,  Yusuke Kanno ,  Yoshio Takazawa

IPC分类号： H03L5/00

CPC分类号： G01R31/31725 ,  G01R31/3004 ,  H01L2924/0002 ,  H01L2924/00

摘要： AVS (Adaptive Voltage Scaling) technique, by which variability and uncertainty are both taken into account. In the system arranged for AVS technique, a detection circuit optimum for each type of process variation is set. Examples of the detection circuit so arranged include a first measurement circuit for detection of variability, which produces a relative value with respect to the gate delay mean value, and a second measurement circuit for detection of uncertainty, which produces a relative value related to the gate delay standard deviation. The first and second measurement circuits are provided separately from each other. The control information for deciding the supply voltage is prepared based on relative values produced by the detection circuits. When preparing the control information, reference is made to e.g. a table data.

摘要翻译： AVS（自适应电压调节）技术，其中考虑了变异性和不确定性。 在安排AVS技术的系统中，设置对于每种类型的处理变化最佳的检测电路。 如此布置的检测电路的示例包括用于检测相对于门延迟平均值的相对值的可变性的第一测量电路和用于检测不确定性的第二测量电路，其产生与门相关的相对值 延迟标准偏差。 第一和第二测量电路彼此分开设置。 用于决定电源电压的控制信息是根据检测电路产生的相对值来准备的。 在准备控制信息时， 一个表数据。

公开(公告)号：US07954023B2

公开(公告)日：2011-05-31

申请号：US12342015

申请日：2008-12-22

申请人： Kazuo Otsuga ,  Kenichi Osada ,  Yusuke Kanno

发明人： Kazuo Otsuga ,  Kenichi Osada ,  Yusuke Kanno

IPC分类号： G01R31/28

CPC分类号： H03K19/0016

摘要： A scan chain configuration and a control method for the same are provided, which are optimized for the leakage current reduction technique by a vector input in SoC in which many functional blocks are mounted. The semiconductor integrated circuit includes: plural power domains (Area1-AreaN) which have plural functional blocks; power switches (PSW1-PSWN) which can supply a power source for operation to the power domains; a scan chain provided for every power domain, and a memory unit (VEC) which supplies, to a scan chain, a vector to enable shifting to a low-leakage state. By re-coupling the scan chain only to a non-operating functional block, it is possible to perform shifting to a low-leakage state for a short time.

摘要翻译： 提供了一种扫描链配置及其控制方法，其通过SoC中的矢量输入针对泄漏电流降低技术进行了优化，其中安装了许多功能块。 半导体集成电路包括：具有多个功能块的多个电力域（Area1-AreaN） 电源开关（PSW1-PSWN），可以向电源区域提供运行的电源; 为每个功率域提供的扫描链，以及向扫描链提供矢量以使其能够转换到低泄漏状态的存储器单元（VEC）。 通过将扫描链重新耦合到非操作功能块，可以在短时间内进行低泄漏状态的切换。

公开(公告)号：US20100301893A1

公开(公告)日：2010-12-02

申请号：US12787090

申请日：2010-05-25

申请人： Kazuo OTSUGA ,  Yusuke Kanno

发明人： Kazuo OTSUGA ,  Yusuke Kanno

IPC分类号： G01R31/26

CPC分类号： G01R31/31721

摘要： In a semiconductor integrated circuit wherein low-threshold-voltage and high-threshold-voltage transistors are disposed mixedly, the operating speed of each transistor can be properly controlled in speed control execution through regulation of a power supply voltage VDD. The semiconductor integrated circuit comprises an internal circuit and measuring circuits. The internal circuit comprises a low-threshold-voltage MOS transistor and a high-threshold-voltage MOS transistor, and the degree of threshold voltage variation of the low-threshold-voltage MOS transistor is larger than the degree of threshold voltage variation of the high-threshold-voltage MOS transistor. The measuring circuit detects which one of fast, typical, and slow states is taken by both the low-threshold-voltage MOS transistor and the high-threshold-voltage MOS transistor. When the result data detected indicates the fast state, the power supply voltage VDD is set to a lower power supply voltage level “VDD−ΔVDD” corresponding to a small variation gradient “β[V/σ]”. When the result data detected indicates the typical state, the power supply voltage VDD is set to an intermediate power supply voltage level “VDD±0”. When the result data detected indicates the slow state, the power supply voltage VDD is set to a higher power supply voltage level “VDD+ΔVDD” corresponding to a large variation gradient “α[V/σ]”.

摘要翻译： 在其中低阈值电压和高阈值电压晶体管被混合地布置的半导体集成电路中，通过调节电源电压VDD可以在速度控制执行中适当地控制每个晶体管的工作速度。 半导体集成电路包括内部电路和测量电路。 内部电路包括低阈值电压MOS晶体管和高阈值电压MOS晶体管，并且低阈值电压MOS晶体管的阈值电压变化程度大于高阈值电压MOS晶体管的阈值电压变化的程度 阈值电压MOS晶体管。 测量电路检测低阈值电压MOS晶体管和高阈值电压MOS晶体管中的哪一个快速，典型和慢速状态。 当检测到的结果数据指示快速状态时，电源电压VDD被设置为对应于小变化梯度“＆bgr; [V /＆sgr]]的较低电源电压电平”VDD-＆Dgr; VDD“。 当检测到的结果数据表示典型状态时，将电源电压VDD设定为中间电源电压电平“VDD±0”。 当检测到的结果数据表示慢速状态时，将电源电压VDD设定为与较大变化梯度“α[V /＆sgr”]对应的较高电源电压电平“VDD +＆Dgr; VDD”。

公开(公告)号：US08248099B2

公开(公告)日：2012-08-21

申请号：US12787090

申请日：2010-05-25

申请人： Kazuo Otsuga ,  Yusuke Kanno

发明人： Kazuo Otsuga ,  Yusuke Kanno

IPC分类号： G01R31/28

CPC分类号： G01R31/31721

摘要： In a semiconductor integrated circuit wherein low-threshold-voltage and high-threshold-voltage transistors are disposed mixedly, the operating speed of each transistor can be properly controlled in speed control execution through regulation of a power supply voltage VDD. The semiconductor integrated circuit comprises an internal circuit and measuring circuits. The internal circuit comprises a low-threshold-voltage MOS transistor and a high-threshold-voltage MOS transistor, and the degree of threshold voltage variation of the low-threshold-voltage MOS transistor is larger than the degree of threshold voltage variation of the high-threshold-voltage MOS transistor. The measuring circuit detects which one of fast, typical, and slow states is taken by both the low-threshold-voltage MOS transistor and the high-threshold-voltage MOS transistor. When the result data detected indicates the fast state, the power supply voltage VDD is set to a lower power supply voltage level “VDD−ΔVDD” corresponding to a small variation gradient “β[V/σ]”. When the result data detected indicates the typical state, the power supply voltage VDD is set to an intermediate power supply voltage level “VDD±0”. When the result data detected indicates the slow state, the power supply voltage VDD is set to a higher power supply voltage level “VDD+ΔVDD” corresponding to a large variation gradient “α[V/σ]”.

摘要翻译： 在其中低阈值电压和高阈值电压晶体管被混合地布置的半导体集成电路中，通过调节电源电压VDD可以在速度控制执行中适当地控制每个晶体管的工作速度。 半导体集成电路包括内部电路和测量电路。 内部电路包括低阈值电压MOS晶体管和高阈值电压MOS晶体管，并且低阈值电压MOS晶体管的阈值电压变化程度大于高阈值电压MOS晶体管的阈值电压变化的程度 阈值电压MOS晶体管。 测量电路检测低阈值电压MOS晶体管和高阈值电压MOS晶体管中的哪一个快速，典型和慢速状态。 当检测到的结果数据指示快速状态时，电源电压VDD被设置为对应于小变化梯度“＆bgr; [V /＆sgr]]的较低电源电压电平”VDD-＆Dgr; VDD“。 当检测到的结果数据表示典型状态时，将电源电压VDD设定为中间电源电压电平“VDD±0”。 当检测到的结果数据表示慢速状态时，将电源电压VDD设定为与较大变化梯度“α[V /＆sgr”]对应的较高电源电压电平“VDD +＆Dgr; VDD”。

公开(公告)号：US20110006792A1

公开(公告)日：2011-01-13

申请号：US12878564

申请日：2010-09-09

申请人： Kazuo Otsuga ,  Tetsuya Yamada ,  Kenichi Osada ,  Yusuke Kanno

发明人： Kazuo Otsuga ,  Tetsuya Yamada ,  Kenichi Osada ,  Yusuke Kanno

IPC分类号： G01R31/3187

CPC分类号： G01R19/0092 ,  Y10T307/406

摘要： A semiconductor integrated circuit is constituted to include a circuit block having a predetermined function, a power switch capable of supplying an operating power to the circuit block, and a current measuring circuit for obtaining a current flowing to the circuit block based on a voltage between terminals of the power switch in a state in which the power switch is turned on and an on-resistance of the power switch. The current flowing to the circuit block is obtained based on the voltage between terminals of the power switch in the state in which the power switch is turned on and the on-resistance of the power switch. Thus, it is possible to measure a current of the circuit block in a state in which a chip is normally operated.

摘要翻译： 半导体集成电路被构成为包括具有预定功能的电路块，能够向电路块提供工作电力的电源开关，以及电流测量电路，用于根据端子之间的电压获得流向电路块的电流 电源开关处于电源开关接通的状态和电源开关的导通电阻。 基于电源开关接通状态和电源开关的导通电阻之间的电源开关电压之间的电流可以获得流向电路块的电流。 因此，可以在芯片正常工作的状态下测量电路块的电流。

公开(公告)号：US20090160544A1

公开(公告)日：2009-06-25

申请号：US12342015

申请日：2008-12-22

申请人： Kazuo Otsuga ,  Kenichi Osada ,  Yusuke Kanno

发明人： Kazuo Otsuga ,  Kenichi Osada ,  Yusuke Kanno

IPC分类号： H01L25/00

CPC分类号： H03K19/0016

摘要： A scan chain configuration and a control method for the same are provided, which are optimized for the leakage current reduction technique by a vector input in SoC in which many functional blocks are mounted. The semiconductor integrated circuit includes: plural power domains (Area1-AreaN) which have plural functional blocks; power switches (PSW1-PSWN) which can supply a power source for operation to the power domains; a scan chain provided for every power domain, and a memory unit (VEC) which supplies, to a scan chain, a vector to enable shifting to a low-leakage state. By re-coupling the scan chain only to a non-operating functional block, it is possible to perform shifting to a low-leakage state for a short time.

摘要翻译： 提供了一种扫描链配置及其控制方法，其通过SoC中的矢量输入针对泄漏电流降低技术进行了优化，其中安装了许多功能块。 半导体集成电路包括：具有多个功能块的多个电力域（Area1-AreaN） 电源开关（PSW1-PSWN），可以向电源区域提供运行的电源; 为每个功率域提供的扫描链，以及向扫描链提供矢量以使其能够转换到低泄漏状态的存储器单元（VEC）。 通过将扫描链重新耦合到非操作功能块，可以在短时间内进行低泄漏状态的切换。

公开(公告)号：US08030956B2

公开(公告)日：2011-10-04

申请号：US12878564

申请日：2010-09-09

申请人： Kazuo Otsuga ,  Tetsuya Yamada ,  Kenichi Osada ,  Yusuke Kanno

发明人： Kazuo Otsuga ,  Tetsuya Yamada ,  Kenichi Osada ,  Yusuke Kanno

IPC分类号： G01R31/3187 ,  G01R31/28

CPC分类号： G01R19/0092 ,  Y10T307/406

摘要： A semiconductor integrated circuit that includes a circuit block having a predetermined function, a power switch capable of supplying an operating power to the circuit block, and a current measuring circuit for obtaining a current flowing to the circuit block based on a voltage between terminals of the power switch in a state in which the power switch is turned on and an on-resistance of the power switch. Thus, it is possible to measure a current of the circuit block in a state in which a chip is normally operated.

摘要翻译： 一种半导体集成电路，包括具有预定功能的电路块，能够向电路块提供工作电力的电源开关，以及电流测量电路，用于根据电流块的端子之间的电压来获得流向电路块的电流 电源开关处于电源开关接通的状态和电源开关的导通电阻。 因此，可以在芯片正常工作的状态下测量电路块的电流。

公开(公告)号：US07812628B2

公开(公告)日：2010-10-12

申请号：US11956122

申请日：2007-12-13

申请人： Kazuo Otsuga ,  Tetsuya Yamada ,  Kenichi Osada ,  Yusuke Kanno

发明人： Kazuo Otsuga ,  Tetsuya Yamada ,  Kenichi Osada ,  Yusuke Kanno

IPC分类号： G01R31/26

CPC分类号： G01R19/0092 ,  Y10T307/406

摘要： A semiconductor integrated circuit is constituted to include a circuit block having a predetermined function, a power switch capable of supplying an operating power to the circuit block, and a current measuring circuit for obtaining a current flowing to the circuit block based on a voltage between terminals of the power switch in a state in which the power switch is turned on and an on-resistance of the power switch. The current flowing to the circuit block is obtained based on the voltage between terminals of the power switch in the state in which the power switch is turned on and the on-resistance of the power switch. Thus, it is possible to measure a current of the circuit block in a state in which a chip is normally operated.

摘要翻译： 半导体集成电路被构成为包括具有预定功能的电路块，能够向电路块提供工作电力的电源开关，以及电流测量电路，用于根据端子之间的电压获得流向电路块的电流 电源开关处于电源开关接通的状态和电源开关的导通电阻。 基于电源开关接通状态和电源开关的导通电阻之间的电源开关电压之间的电流可以获得流向电路块的电流。 因此，可以在芯片正常工作的状态下测量电路块的电流。

公开(公告)号：US20080143184A1

公开(公告)日：2008-06-19

申请号：US11956122

申请日：2007-12-13

申请人： Kazuo OTSUGA ,  Tetsuya Yamada ,  Kenichi Osada ,  Yusuke Kanno

发明人： Kazuo OTSUGA ,  Tetsuya Yamada ,  Kenichi Osada ,  Yusuke Kanno

IPC分类号： H02J1/00 ,  G01R19/00

CPC分类号： G01R19/0092 ,  Y10T307/406

摘要： A semiconductor integrated circuit is constituted to include a circuit block having a predetermined function, a power switch capable of supplying an operating power to the circuit block, and a current measuring circuit for obtaining a current flowing to the circuit block based on a voltage between terminals of the power switch in a state in which the power switch is turned on and an on-resistance of the power switch. The current flowing to the circuit block is obtained based on the voltage between terminals of the power switch in the state in which the power switch is turned on and the on-resistance of the power switch. Thus, it is possible to measure a current of the circuit block in a state in which a chip is normally operated.

摘要翻译： 半导体集成电路被构成为包括具有预定功能的电路块，能够向电路块提供工作电力的电源开关，以及电流测量电路，用于根据端子之间的电压获得流向电路块的电流 电源开关处于电源开关接通的状态和电源开关的导通电阻。 基于电源开关接通状态和电源开关的导通电阻之间的电源开关电压之间的电流可以获得流向电路块的电流。 因此，可以在芯片正常工作的状态下测量电路块的电流。