公开(公告)号：US08030956B2

公开(公告)日：2011-10-04

申请号：US12878564

申请日：2010-09-09

申请人： Kazuo Otsuga ,  Tetsuya Yamada ,  Kenichi Osada ,  Yusuke Kanno

发明人： Kazuo Otsuga ,  Tetsuya Yamada ,  Kenichi Osada ,  Yusuke Kanno

IPC分类号： G01R31/3187 ,  G01R31/28

CPC分类号： G01R19/0092 ,  Y10T307/406

摘要： A semiconductor integrated circuit that includes a circuit block having a predetermined function, a power switch capable of supplying an operating power to the circuit block, and a current measuring circuit for obtaining a current flowing to the circuit block based on a voltage between terminals of the power switch in a state in which the power switch is turned on and an on-resistance of the power switch. Thus, it is possible to measure a current of the circuit block in a state in which a chip is normally operated.

摘要翻译： 一种半导体集成电路，包括具有预定功能的电路块，能够向电路块提供工作电力的电源开关，以及电流测量电路，用于根据电流块的端子之间的电压来获得流向电路块的电流 电源开关处于电源开关接通的状态和电源开关的导通电阻。 因此，可以在芯片正常工作的状态下测量电路块的电流。

公开(公告)号：US07812628B2

公开(公告)日：2010-10-12

申请号：US11956122

申请日：2007-12-13

申请人： Kazuo Otsuga ,  Tetsuya Yamada ,  Kenichi Osada ,  Yusuke Kanno

发明人： Kazuo Otsuga ,  Tetsuya Yamada ,  Kenichi Osada ,  Yusuke Kanno

IPC分类号： G01R31/26

CPC分类号： G01R19/0092 ,  Y10T307/406

摘要： A semiconductor integrated circuit is constituted to include a circuit block having a predetermined function, a power switch capable of supplying an operating power to the circuit block, and a current measuring circuit for obtaining a current flowing to the circuit block based on a voltage between terminals of the power switch in a state in which the power switch is turned on and an on-resistance of the power switch. The current flowing to the circuit block is obtained based on the voltage between terminals of the power switch in the state in which the power switch is turned on and the on-resistance of the power switch. Thus, it is possible to measure a current of the circuit block in a state in which a chip is normally operated.

摘要翻译： 半导体集成电路被构成为包括具有预定功能的电路块，能够向电路块提供工作电力的电源开关，以及电流测量电路，用于根据端子之间的电压获得流向电路块的电流 电源开关处于电源开关接通的状态和电源开关的导通电阻。 基于电源开关接通状态和电源开关的导通电阻之间的电源开关电压之间的电流可以获得流向电路块的电流。 因此，可以在芯片正常工作的状态下测量电路块的电流。

公开(公告)号：US20080143184A1

公开(公告)日：2008-06-19

申请号：US11956122

申请日：2007-12-13

申请人： Kazuo OTSUGA ,  Tetsuya Yamada ,  Kenichi Osada ,  Yusuke Kanno

发明人： Kazuo OTSUGA ,  Tetsuya Yamada ,  Kenichi Osada ,  Yusuke Kanno

IPC分类号： H02J1/00 ,  G01R19/00

CPC分类号： G01R19/0092 ,  Y10T307/406

摘要： A semiconductor integrated circuit is constituted to include a circuit block having a predetermined function, a power switch capable of supplying an operating power to the circuit block, and a current measuring circuit for obtaining a current flowing to the circuit block based on a voltage between terminals of the power switch in a state in which the power switch is turned on and an on-resistance of the power switch. The current flowing to the circuit block is obtained based on the voltage between terminals of the power switch in the state in which the power switch is turned on and the on-resistance of the power switch. Thus, it is possible to measure a current of the circuit block in a state in which a chip is normally operated.

摘要翻译： 半导体集成电路被构成为包括具有预定功能的电路块，能够向电路块提供工作电力的电源开关，以及电流测量电路，用于根据端子之间的电压获得流向电路块的电流 电源开关处于电源开关接通的状态和电源开关的导通电阻。 基于电源开关接通状态和电源开关的导通电阻之间的电源开关电压之间的电流可以获得流向电路块的电流。 因此，可以在芯片正常工作的状态下测量电路块的电流。

公开(公告)号：US20110006792A1

公开(公告)日：2011-01-13

申请号：US12878564

申请日：2010-09-09

申请人： Kazuo Otsuga ,  Tetsuya Yamada ,  Kenichi Osada ,  Yusuke Kanno

发明人： Kazuo Otsuga ,  Tetsuya Yamada ,  Kenichi Osada ,  Yusuke Kanno

IPC分类号： G01R31/3187

CPC分类号： G01R19/0092 ,  Y10T307/406

摘要： A semiconductor integrated circuit is constituted to include a circuit block having a predetermined function, a power switch capable of supplying an operating power to the circuit block, and a current measuring circuit for obtaining a current flowing to the circuit block based on a voltage between terminals of the power switch in a state in which the power switch is turned on and an on-resistance of the power switch. The current flowing to the circuit block is obtained based on the voltage between terminals of the power switch in the state in which the power switch is turned on and the on-resistance of the power switch. Thus, it is possible to measure a current of the circuit block in a state in which a chip is normally operated.

摘要翻译： 半导体集成电路被构成为包括具有预定功能的电路块，能够向电路块提供工作电力的电源开关，以及电流测量电路，用于根据端子之间的电压获得流向电路块的电流 电源开关处于电源开关接通的状态和电源开关的导通电阻。 基于电源开关接通状态和电源开关的导通电阻之间的电源开关电压之间的电流可以获得流向电路块的电流。 因此，可以在芯片正常工作的状态下测量电路块的电流。

公开(公告)号：US07954023B2

公开(公告)日：2011-05-31

申请号：US12342015

申请日：2008-12-22

申请人： Kazuo Otsuga ,  Kenichi Osada ,  Yusuke Kanno

发明人： Kazuo Otsuga ,  Kenichi Osada ,  Yusuke Kanno

IPC分类号： G01R31/28

CPC分类号： H03K19/0016

摘要： A scan chain configuration and a control method for the same are provided, which are optimized for the leakage current reduction technique by a vector input in SoC in which many functional blocks are mounted. The semiconductor integrated circuit includes: plural power domains (Area1-AreaN) which have plural functional blocks; power switches (PSW1-PSWN) which can supply a power source for operation to the power domains; a scan chain provided for every power domain, and a memory unit (VEC) which supplies, to a scan chain, a vector to enable shifting to a low-leakage state. By re-coupling the scan chain only to a non-operating functional block, it is possible to perform shifting to a low-leakage state for a short time.

摘要翻译： 提供了一种扫描链配置及其控制方法，其通过SoC中的矢量输入针对泄漏电流降低技术进行了优化，其中安装了许多功能块。 半导体集成电路包括：具有多个功能块的多个电力域（Area1-AreaN） 电源开关（PSW1-PSWN），可以向电源区域提供运行的电源; 为每个功率域提供的扫描链，以及向扫描链提供矢量以使其能够转换到低泄漏状态的存储器单元（VEC）。 通过将扫描链重新耦合到非操作功能块，可以在短时间内进行低泄漏状态的切换。

公开(公告)号：US20090160544A1

公开(公告)日：2009-06-25

申请号：US12342015

申请日：2008-12-22

申请人： Kazuo Otsuga ,  Kenichi Osada ,  Yusuke Kanno

发明人： Kazuo Otsuga ,  Kenichi Osada ,  Yusuke Kanno

IPC分类号： H01L25/00

CPC分类号： H03K19/0016

摘要： A scan chain configuration and a control method for the same are provided, which are optimized for the leakage current reduction technique by a vector input in SoC in which many functional blocks are mounted. The semiconductor integrated circuit includes: plural power domains (Area1-AreaN) which have plural functional blocks; power switches (PSW1-PSWN) which can supply a power source for operation to the power domains; a scan chain provided for every power domain, and a memory unit (VEC) which supplies, to a scan chain, a vector to enable shifting to a low-leakage state. By re-coupling the scan chain only to a non-operating functional block, it is possible to perform shifting to a low-leakage state for a short time.

摘要翻译： 提供了一种扫描链配置及其控制方法，其通过SoC中的矢量输入针对泄漏电流降低技术进行了优化，其中安装了许多功能块。 半导体集成电路包括：具有多个功能块的多个电力域（Area1-AreaN） 电源开关（PSW1-PSWN），可以向电源区域提供运行的电源; 为每个功率域提供的扫描链，以及向扫描链提供矢量以使其能够转换到低泄漏状态的存储器单元（VEC）。 通过将扫描链重新耦合到非操作功能块，可以在短时间内进行低泄漏状态的切换。

公开(公告)号：US07899643B2

公开(公告)日：2011-03-01

申请号：US11935790

申请日：2007-11-06

申请人： Makoto Saen ,  Kenichi Osada ,  Tetsuya Yamada ,  Yusuke Kanno ,  Satoshi Misaka

发明人： Makoto Saen ,  Kenichi Osada ,  Tetsuya Yamada ,  Yusuke Kanno ,  Satoshi Misaka

IPC分类号： G01K1/12 ,  G06F19/00

CPC分类号： G06F1/3228 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor integrated circuit device which consumes less power and enables real-time processing. The semiconductor integrated circuit device includes thermal sensors which detect temperature and determine whether the detection result exceeds reference values and output the result, and a control block capable of controlling the operations of arithmetic blocks based on the output signals of the thermal sensors. The control block returns to an operation state from a suspended state with an interrupt signal based on the output signals of the thermal sensors and determines the operation conditions of the arithmetic blocks to ensure that the temperature conditions of the arithmetic blocks are satisfied. Thereby, power consumption is reduced and real-time processing efficiency is improved.

摘要翻译： 一种半导体集成电路器件，其消耗较少功率并实现实时处理。 半导体集成电路装置包括检测温度并确定检测结果是否超过参考值并输出结果的热传感器，以及能够基于热传感器的输出信号来控制运算块的操作的控制块。 控制块基于热传感器的输出信号从具有中断信号的挂起状态返回到操作状态，并且确定运算块的操作条件，以确保运算块的温度条件得到满足。 从而降低了功耗，提高了实时处理效率。

公开(公告)号：US20080114967A1

公开(公告)日：2008-05-15

申请号：US11935790

申请日：2007-11-06

申请人： Makoto Saen ,  Kenichi Osada ,  Tetsuya Yamada ,  Yusuke Kanno ,  Satoshi Misaka

发明人： Makoto Saen ,  Kenichi Osada ,  Tetsuya Yamada ,  Yusuke Kanno ,  Satoshi Misaka

IPC分类号： G06F9/302

CPC分类号： G06F1/3228 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a semiconductor integrated circuit device which consumes less power and enables real-time processing. The semiconductor integrated circuit device comprises: thermal sensors which can detect temperature, determine whether the detection result exceeds each of the above reference values and output the result; and a control block capable of controlling the operations of arithmetic blocks based on the output signals of the thermal sensors, wherein the control block returns to an operation state from a suspended state with an interrupt signal based on the output signals of the thermal sensors and determines the operation conditions of the arithmetic blocks to ensure that the temperature conditions of the arithmetic blocks are satisfied. Thereby, power consumption is reduced and real-time processing efficiency is improved.

摘要翻译： 提供了一种半导体集成电路器件，其消耗较少功率并实现实时处理。 半导体集成电路装置包括：可以检测温度的热传感器，确定检测结果是否超过上述参考值，并输出结果; 以及控制块，其能够基于所述热传感器的输出信号来控制运算块的运算，其中，所述控制块基于所述热传感器的输出信号，利用中断信号从暂停状态返回到运行状态，并且确定 运算块的操作条件，以确保运算块的温度条件得到满足。 从而降低了功耗，提高了实时处理效率。

公开(公告)号：US07994822B2

公开(公告)日：2011-08-09

申请号：US12690659

申请日：2010-01-20

申请人： Kazuo Otsuga ,  Kenichi Osada ,  Makoto Saen

发明人： Kazuo Otsuga ,  Kenichi Osada ,  Makoto Saen

IPC分类号： H03K19/00

CPC分类号： H03L7/0812 ,  G06F1/12 ,  H01L25/18 ,  H01L2224/48137 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H03K5/15033 ,  H03L7/07

摘要： The performance of a whole system is improved by synchronizing communication and computations between stacked computing LSIs. Each of stacked an external communication LSI and a computing LSI has a PLL which multiplies a crystal oscillator clock signal, a clock pulse generator which distributes the clock signal, and flip-flop circuits. The computing LSI has a DLL circuit composed of a clock phase comparator, a delay controller, and a delay chain. In order to synchronize the communication and computations of the external communication LSI and the computing LSI, a synchronization reference clock signal is transmitted from the external communication LSI to the computing LSI via a through-electrode. An internal clock signal of the computing LSI is synchronized with the synchronization reference clock signal from the external communication LSI by the DLL circuit.

摘要翻译： 通过在堆叠的计算LSI之间同步通信和计算，可以提高整个系统的性能。 堆叠的外部通信LSI和计算LSI中的每一个具有将晶体振荡器时钟信号相乘的PLL，分配时钟信号的时钟脉冲发生器和触发器电路。 计算LSI具有由时钟相位比较器，延迟控制器和延迟链组成的DLL电路。 为了同步外部通信LSI和计算LSI的通信和计算，同步参考时钟信号从外部通信LSI经由通孔发送到计算LSI。 计算LSI的内部时钟信号与来自外部通信LSI的同步基准时钟信号通过DLL电路同步。

公开(公告)号：US20100182046A1

公开(公告)日：2010-07-22

申请号：US12690659

申请日：2010-01-20

申请人： Kazuo Otsuga ,  Kenichi Osada ,  Makoto Saen

发明人： Kazuo Otsuga ,  Kenichi Osada ,  Makoto Saen

IPC分类号： H03K19/00

CPC分类号： H03L7/0812 ,  G06F1/12 ,  H01L25/18 ,  H01L2224/48137 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H03K5/15033 ,  H03L7/07

摘要： The performance of a whole system is improved by synchronizing communication and computations between stacked computing LSIs. Each of stacked an external communication LSI and a computing LSI has a PLL which multiplies a crystal oscillator clock signal, a clock pulse generator which distributes the clock signal, and flip-flop circuits. The computing LSI has a DLL circuit composed of a clock phase comparator, a delay controller, and a delay chain. In order to synchronize the communication and computations of the external communication LSI and the computing LSI, a synchronization reference clock signal is transmitted from the external communication LSI to the computing LSI via a through-electrode. An internal clock signal of the computing LSI is synchronized with the synchronization reference clock signal from the external communication LSI by the DLL circuit.

摘要翻译： 通过在堆叠的计算LSI之间同步通信和计算，可以提高整个系统的性能。 堆叠的外部通信LSI和计算LSI中的每一个具有将晶体振荡器时钟信号相乘的PLL，分配时钟信号的时钟脉冲发生器和触发器电路。 计算LSI具有由时钟相位比较器，延迟控制器和延迟链组成的DLL电路。 为了同步外部通信LSI和计算LSI的通信和计算，同步参考时钟信号从外部通信LSI经由通孔发送到计算LSI。 计算LSI的内部时钟信号与来自外部通信LSI的同步基准时钟信号通过DLL电路同步。