公开(公告)号：US20230297255A1

公开(公告)日：2023-09-21

申请号：US17931265

申请日：2022-09-12

Applicant: Kioxia Corporation

Inventor： Keita KIMURA ,  Kenri NAKAI

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0679

Abstract: According to one embodiment, a semiconductor memory device includes memory cells and a control circuit configured to control an erase operation on the memory cells. The control circuit sequentially executes, in the erase operation, a first erase process, a first erase verify process, a second erase process, and a second erase verify process on the memory cells, acquires, in the first erase verify process, first memory cells having a threshold voltage equal to or lower than a first verify voltage, from among the memory cells, acquires, in the second erase verify process, the number of second memory cells having a threshold voltage higher than the first verify voltage, from among the first memory cells, and determines whether the number of the second memory cells is larger than a first value or not.

公开(公告)号：US20210065774A1

公开(公告)日：2021-03-04

申请号：US16807078

申请日：2020-03-02

Applicant: KIOXIA CORPORATION

Inventor： Keita KIMURA ,  Kenri NAKAI ,  Mario SAKO

IPC: G11C11/4076 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/408 ,  G11C7/10 ,  G11C7/22

Abstract: A semiconductor storage device includes first, second, and third transistors, first, second, and third bit lines connected to the first, second, and third transistors, a word line connected to the first, second, and third transistors, and a control circuit configured to perform a program operation for writing data to the second and third transistors, including raising a first voltage applied to the first bit line at a first timing, raising a second voltage applied to the word line at a second timing, raising a third voltage applied to the second bit line at a third timing, raising a fourth voltage applied to the third bit line at a fourth timing, and lowering the first voltage at a fifth timing. The first voltage is raised to a first predetermined voltage, and each of the third and fourth voltages is raised to a second predetermined voltage smaller than the first predetermined voltage.