公开(公告)号：US20220020440A1

公开(公告)日：2022-01-20

申请号：US17188687

申请日：2021-03-01

Applicant: KIOXIA CORPORATION

Inventor： Keita KIMURA

IPC: G11C16/34 ,  G11C16/04 ,  G11C5/02 ,  H01L27/11556 ,  G11C16/26

Abstract: A semiconductor storage device includes memory strings, bit lines connected to the memory strings, respectively, sense transistors of which gates are connected to the bit lines, respectively, first transistors connected between the bit lines and the gates of the sense transistors, respectively, and a control circuit. Each of the memory strings includes first and second memory transistors adjacent to each other. The control circuit is configured to perform, during a first write sequence, a read operation with respect to the second memory transistors, a program operation with respect to the first memory transistors, and a verify operation with respect to the first memory transistors, in this order. During the verify operation, the control circuit turns on the first transistors during a first sense period, and then turns on the first transistors during a second sense period longer than the first sense period.

公开(公告)号：US20210065774A1

公开(公告)日：2021-03-04

申请号：US16807078

申请日：2020-03-02

Applicant: KIOXIA CORPORATION

Inventor： Keita KIMURA ,  Kenri NAKAI ,  Mario SAKO

IPC: G11C11/4076 ,  G11C11/4074 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/408 ,  G11C7/10 ,  G11C7/22

Abstract: A semiconductor storage device includes first, second, and third transistors, first, second, and third bit lines connected to the first, second, and third transistors, a word line connected to the first, second, and third transistors, and a control circuit configured to perform a program operation for writing data to the second and third transistors, including raising a first voltage applied to the first bit line at a first timing, raising a second voltage applied to the word line at a second timing, raising a third voltage applied to the second bit line at a third timing, raising a fourth voltage applied to the third bit line at a fourth timing, and lowering the first voltage at a fifth timing. The first voltage is raised to a first predetermined voltage, and each of the third and fourth voltages is raised to a second predetermined voltage smaller than the first predetermined voltage.

公开(公告)号：US20240096417A1

公开(公告)日：2024-03-21

申请号：US18337605

申请日：2023-06-20

Applicant: Kioxia Corporation

Inventor： Hiroshi MAEJIMA ,  Katsuaki ISOBE ,  Keita KIMURA

IPC: G11C16/04 ,  G11C5/06 ,  G11C16/14 ,  G11C16/26

CPC classification number: G11C16/0483 ,  G11C5/063 ,  G11C16/14 ,  G11C16/26

Abstract: In one embodiment, a semiconductor storage device includes a string that has one end electrically connected to a bit line, and another end electrically connected to a source line, and includes a plurality of memory cells. An operation of writing data to each of a plurality of adjacent first memory cells among the plurality of memory cells is sequentially performed in a direction from a first memory cell on a side of the source line to a first memory cell on a side of the bit line. An operation of reading data from each of the plurality of adjacent first memory cells is performed to allow a current to flow through the string in a first direction from the source line to the bit line.

公开(公告)号：US20230297255A1

公开(公告)日：2023-09-21

申请号：US17931265

申请日：2022-09-12

Applicant: Kioxia Corporation

Inventor： Keita KIMURA ,  Kenri NAKAI

IPC: G06F3/06

CPC classification number: G06F3/0625 ,  G06F3/0653 ,  G06F3/0679

Abstract: According to one embodiment, a semiconductor memory device includes memory cells and a control circuit configured to control an erase operation on the memory cells. The control circuit sequentially executes, in the erase operation, a first erase process, a first erase verify process, a second erase process, and a second erase verify process on the memory cells, acquires, in the first erase verify process, first memory cells having a threshold voltage equal to or lower than a first verify voltage, from among the memory cells, acquires, in the second erase verify process, the number of second memory cells having a threshold voltage higher than the first verify voltage, from among the first memory cells, and determines whether the number of the second memory cells is larger than a first value or not.