公开(公告)号：US20230056364A1

公开(公告)日：2023-02-23

申请号：US17654136

申请日：2022-03-09

Applicant: KIOXIA CORPORATION

Inventor： Manabu SAKANIWA ,  Yasuhiro SHIINO ,  Kota NISHIKAWA ,  Yu ISHIYAMA ,  Shinji SUZUKI

IPC: G11C16/16 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04

Abstract: A semiconductor memory device includes a substrate, gate electrodes, a semiconductor layer opposed to gate electrodes, an electric charge accumulating layer disposed between gate electrodes and the semiconductor layer, a conductive layer connected to one end portion of the semiconductor layer, and a control circuit electrically connected to gate electrodes and the conductive layer. Gate electrodes include first gate electrodes, second gate electrodes, and third gate electrode. The control circuit is configured to perform an erase operation. The erase operation includes: at least one-time first operation that applies a first voltage to the conductive layer; a second operation performed after the first operation, the second operation applying a second voltage to the third gate electrode; and at least one-time third operation performed after the second operation, the third operation applying a third voltage same as or larger than the first voltage to the conductive layer.

公开(公告)号：US20240096422A1

公开(公告)日：2024-03-21

申请号：US18459745

申请日：2023-09-01

Applicant: Kioxia Corporation

Inventor： Hiroaki KOSAKO ,  Kota NISHIKAWA ,  Kenrou KIKUCHI

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/3445

Abstract: A first select transistor is connected to a first wiring. A first memory cell transistor and a second memory cell transistor are connected in series between the first select transistor and a second select transistor. A first word line is connected to the first memory cell transistor. A second word line is connected to the second memory cell transistor. During a first period in which the first voltage is applied to the first wiring, a second voltage lower than a first voltage is applied in parallel to the first word line and the second word line. During a second period in which a third voltage higher than the first voltage is applied to the first wiring, the second voltage is applied to the first word line, and a fourth voltage higher than the second voltage and lower than the third voltage is applied to the second word line. During a third period in which the third voltage is applied to the first wiring, the fourth voltage is applied to the first word line, and the second voltage is applied to the second word line.