公开(公告)号：US20230064140A1

公开(公告)日：2023-03-02

申请号：US17686835

申请日：2022-03-04

Applicant: Kioxia Corporation

Inventor： Yasuhiro SHIINO ,  Masahiko IGA ,  Shinji SUZUKI

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C7/08 ,  G11C7/10

Abstract: A second conductor, third conductor, and fourth conductor sandwiches a first layer together with a first semiconductor. The fourth conductor is positioned farther from the first conductor than the third conductor, which is positioned farther from first conductor than the second conductor. A first circuit is configured to apply a first potential to the first and second conductors, apply a second potential lower than the first potential to the third conductor in parallel with the application of the first potential, and apply a third potential higher than the second potential and lower than the first potential to the fourth conductor in parallel with the application of the first potential.

公开(公告)号：US20210193239A1

公开(公告)日：2021-06-24

申请号：US17011747

申请日：2020-09-03

Applicant: KIOXIA CORPORATION

Inventor： Shinji SUZUKI ,  Yasuhiro SHIMURA

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30

Abstract: A semiconductor storage device includes memory cells a controller performing a write operation on the memory cells. The write operation includes program loops with a program operation and a verification operation. In a first loop the controller applies a first program voltage and a first verification voltage. Next, a detection operation counts the memory cells with a threshold voltage above a first threshold value. In a second program loop, after the detection operation, the controller applies a second program voltage and a second verification voltage. The values of used for second program voltage and the second verification voltage are set dependent on the counted number of memory cells with a threshold voltage above the first threshold value.

公开(公告)号：US20210082505A1

公开(公告)日：2021-03-18

申请号：US16926977

申请日：2020-07-13

Applicant: Kioxia Corporation

Inventor： Shinji SUZUKI

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  G11C16/24 ,  G11C16/16

Abstract: A semiconductor device according to an embodiment includes first and second drain select transistors, first and second source select transistors, first and second memory cell transistors, third and fourth memory cell transistors, first and second bit lines, first to third select gate line, first and second word lines, and a controller. The controller is configured to execute, in the program loop, a program operation, a recovery operation and a verify operation in sequence. In the write operation of the first memory cell transistor, the controller is configured, at a first time of the recovery operation, to: apply a first voltage to the first select gate line; apply a second voltage to the third select gate line; and apply a third voltage to the first bit line.

公开(公告)号：US20230069683A1

公开(公告)日：2023-03-02

申请号：US17983459

申请日：2022-11-09

Applicant: Kioxia Corporation

Inventor： Shinji SUZUKI

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/24 ,  G11C16/32 ,  G11C16/30 ,  G11C16/26

Abstract: A method of adjusting operating conditions includes: a substrate; first conductive layers; a first semiconductor layers facing the first conductive layers; a second semiconductor layer connected to the first semiconductor layers; and an electric charge accumulating layer disposed between the first conductive layers and the first semiconductor layers. At a predetermined timing of a program operation, the second conductive layer which is one of the first conductive layers is supplied with a program voltage or a write pass voltage. The method executes: a first operation that supplies the second conductive layer with the write pass voltage and supplies a third conductive layer which is one of the plurality of first conductive layers with the program voltage; and a second operation that supplies the second conductive layer with a verify voltage and supplies the third conductive layer with a voltage.

公开(公告)号：US20210090659A1

公开(公告)日：2021-03-25

申请号：US16934082

申请日：2020-07-21

Applicant: Kioxia Corporation

Inventor： Shinji SUZUKI

IPC: G11C16/14 ,  G11C16/26 ,  G11C16/08 ,  G11C16/30 ,  G11C16/34

Abstract: According to one embodiment, a memory system includes: a memory device including a memory cell transistor; and a controller configured to make first data inaccessible from an outside of the memory system without erasing the first data, and increase a threshold voltage of the memory cell transistor, before determining to write data into the memory cell transistor. The controller is further configured to decrease, after determining to write second data into the memory cell transistor, the threshold voltage of the memory cell transistor to bring the memory cell transistor into an erase state; and write, after bringing the memory cell transistor into the erase state, the second data into the memory cell transistor.

公开(公告)号：US20230056364A1

公开(公告)日：2023-02-23

申请号：US17654136

申请日：2022-03-09

Applicant: KIOXIA CORPORATION

Inventor： Manabu SAKANIWA ,  Yasuhiro SHIINO ,  Kota NISHIKAWA ,  Yu ISHIYAMA ,  Shinji SUZUKI

IPC: G11C16/16 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04

Abstract: A semiconductor memory device includes a substrate, gate electrodes, a semiconductor layer opposed to gate electrodes, an electric charge accumulating layer disposed between gate electrodes and the semiconductor layer, a conductive layer connected to one end portion of the semiconductor layer, and a control circuit electrically connected to gate electrodes and the conductive layer. Gate electrodes include first gate electrodes, second gate electrodes, and third gate electrode. The control circuit is configured to perform an erase operation. The erase operation includes: at least one-time first operation that applies a first voltage to the conductive layer; a second operation performed after the first operation, the second operation applying a second voltage to the third gate electrode; and at least one-time third operation performed after the second operation, the third operation applying a third voltage same as or larger than the first voltage to the conductive layer.

公开(公告)号：US20220059175A1

公开(公告)日：2022-02-24

申请号：US17197541

申请日：2021-03-10

Applicant: Kioxia Corporation

Inventor： Shinji SUZUKI

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/32 ,  G11C16/30 ,  G11C16/24

Abstract: A method of adjusting operating conditions includes: a substrate; first conductive layers; a first semiconductor layers facing the first conductive layers; a second semiconductor layer connected to the first semiconductor layers; and an electric charge accumulating layer disposed between the first conductive layers and the first semiconductor layers. At a predetermined timing of a program operation, the second conductive layer which is one of the first conductive layers is supplied with a program voltage or a write pass voltage. The method executes: a first operation that supplies the second conductive layer with the write pass voltage and supplies a third conductive layer which is one of the plurality of first conductive layers with the program voltage; and a second operation that supplies the second conductive layer with a verify voltage and supplies the third conductive layer with a voltage.