公开(公告)号：US20240096422A1

公开(公告)日：2024-03-21

申请号：US18459745

申请日：2023-09-01

Applicant: Kioxia Corporation

Inventor： Hiroaki KOSAKO ,  Kota NISHIKAWA ,  Kenrou KIKUCHI

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/3445

Abstract: A first select transistor is connected to a first wiring. A first memory cell transistor and a second memory cell transistor are connected in series between the first select transistor and a second select transistor. A first word line is connected to the first memory cell transistor. A second word line is connected to the second memory cell transistor. During a first period in which the first voltage is applied to the first wiring, a second voltage lower than a first voltage is applied in parallel to the first word line and the second word line. During a second period in which a third voltage higher than the first voltage is applied to the first wiring, the second voltage is applied to the first word line, and a fourth voltage higher than the second voltage and lower than the third voltage is applied to the second word line. During a third period in which the third voltage is applied to the first wiring, the fourth voltage is applied to the first word line, and the second voltage is applied to the second word line.

公开(公告)号：US20210074359A1

公开(公告)日：2021-03-11

申请号：US17004272

申请日：2020-08-27

Applicant: Kioxia Corporation

Inventor： Kenrou KIKUCHI ,  Yasuhiro SHIMURA

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C11/56

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of NAND strings, each of the plurality of NAND strings including a plurality of memory cell transistors connected to each other in series; a plurality of word lines commonly connected to the plurality of memory strings and connected to the plurality of memory cell transistors, respectively; and a row decoder configured to supply a predetermined voltage higher than a ground voltage to each of the plurality of word lines after a program operation for writing data to a selected word line is completed.

公开(公告)号：US20230186991A1

公开(公告)日：2023-06-15

申请号：US18106520

申请日：2023-02-07

Applicant: Kioxia Corporation

Inventor： Kenrou KIKUCHI ,  Yasuhiro SHIMURA

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C11/56 ,  G11C16/26 ,  G11C16/30 ,  G11C16/24

CPC classification number: G11C16/0483 ,  G11C16/10 ,  G11C16/08 ,  G11C11/5642 ,  G11C16/26 ,  G11C16/30 ,  G11C11/5628 ,  G11C16/24

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of NAND strings, each of the plurality of NAND strings including a plurality of memory cell transistors connected to each other in series; a plurality of word lines commonly connected to the plurality of memory strings and connected to the plurality of memory cell transistors, respectively; and a row decoder configured to supply a predetermined voltage higher than a ground voltage to each of the plurality of word lines after a program operation for writing data to a selected word line is completed.

公开(公告)号：US20240203498A1

公开(公告)日：2024-06-20

申请号：US18591563

申请日：2024-02-29

Applicant: KIOXIA CORPORATION

Inventor： Kenrou KIKUCHI ,  Yasuhiro SHIMURA

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

CPC classification number: G11C16/0483 ,  G11C11/5628 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: A semiconductor memory device includes: a memory cell array including a plurality of NAND strings, each of the plurality of NAND strings including a plurality of memory cell transistors connected to each other in series; a plurality of word lines commonly connected to the plurality of memory strings and connected to the plurality of memory cell transistors, respectively; and a row decoder configured to supply a predetermined voltage higher than a ground voltage to each of the plurality of word lines after a program operation for writing data to a selected word line is completed.

公开(公告)号：US20240079065A1

公开(公告)日：2024-03-07

申请号：US18446106

申请日：2023-08-08

Applicant: Kioxia Corporation

Inventor： Yasuhiro SHIINO ,  Kenrou KIKUCHI

IPC: G11C16/10 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26

CPC classification number: G11C16/102 ,  G11C16/08 ,  G11C16/16 ,  G11C16/26

Abstract: According to one embodiment, a semiconductor memory device includes a first memory sub-block and a second memory sub-block arranged in a first direction and a control circuit. The first memory sub-block includes a first memory cell and a first word line connected to the first memory cell. The second memory sub-block includes a second memory cell and a second word line connected to the second memory cell. The control circuit executes a first and a second write operation on the first memory cell. In the first write operation, the control circuit applies a program voltage to the first word line and a first unselect write voltage to the second word line. In the second write operation, the program voltage is applied to the first word line and a second unselect write voltage is applied to the second word line.