公开(公告)号：US20240419536A1

公开(公告)日：2024-12-19

申请号：US18743554

申请日：2024-06-14

Applicant: Kioxia Corporation

Inventor： Masaki NAKAMURA

IPC: G06F11/10

Abstract: A memory controller includes a memory interface circuit, a memory device, and an error correction circuit. The memory interface circuit receives, during a read operation executed in a semiconductor memory device, a data signal from the semiconductor memory device to acquire the data from the data signal. The error correction circuit is configured to store in the memory device likelihood information of the data acquired from the data signal, revise the likelihood information of the data acquired from the data signal, and perform an error correction process on the data based on the revised likelihood information.

公开(公告)号：US20240324220A1

公开(公告)日：2024-09-26

申请号：US18604848

申请日：2024-03-14

Applicant: KIOXIA CORPORATION

Inventor： Yoshikazu HOSOMURA ,  Go OIKE ,  Yutaka SHIMIZU ,  Masaki NAKAMURA ,  Hironobu HAMANAKA ,  Hideo WADA

IPC: H10B43/27 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H10B80/00 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor memory device comprises: a substrate; a first wiring layer; a second wiring layer provided between the substrate and the first wiring layer; and a memory cell array layer provided between the substrate and the second wiring layer. The memory cell array layer comprises a contact extending in a first direction intersecting with a surface of the substrate. The first wiring layer has a second conductive layer that includes a connecting portion, a pad electrode portion, and a peripheral edge portion. The connecting portion is connected to one end in the first direction of the contact. The second wiring layer has: a first opening which is provided in a region including the connecting portion and the pad electrode portion of the second conductive layer; and a ring-shaped first slit which surrounds the peripheral edge portion of the second conductive layer.

公开(公告)号：US20210091060A1

公开(公告)日：2021-03-25

申请号：US17003928

申请日：2020-08-26

Applicant: KIOXIA CORPORATION

Inventor： Masaki NAKAMURA

IPC: H01L25/18 ,  H01L25/00 ,  H01L23/00

Abstract: According to one embodiment, a storage device includes a first die and a second die. The first die is stacked on the second die. The first die includes a plurality of die regions partitioned by dicing regions. Each of the die regions includes a memory cell array. The second die includes a circuit configured to process reading of data from and writing of data to, memory cells in the memory cell arrays in each of the die regions of the first die.