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    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE
    2.
    发明申请
    NON-VOLATILE SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210057028A1

    公开(公告)日：2021-02-25

    申请号：US16810910

    申请日：2020-03-06

    Applicant: Kioxia Corporation

    Inventor： Yoshikazu HOSOMURA

    IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  H01L27/11582 ,  H01L27/11565

    Abstract: According to the present embodiment, a semiconductor memory device includes a first memory bunch including a first source line, a first source side selecting gate transistor, a first source side selecting gate line, a plurality of first non-volatile memory cells, a plurality of first word lines, a first drain side selecting gate transistor, a first drain side selecting gate line, and a first bit line; a second memory bunch including, a second source line, a second source side selecting gate transistor, a second source side selecting gate line, a plurality of second non-volatile memory cells, a plurality of second word lines, a second drain side selecting gate transistor, a second drain side selecting gate line, and a second bit line; a common bit line; a first bit line transfer transistor; and a second bit line transfer transistor.

    SEMICONDUCTOR MEMORY DEVICE
    3.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240071478A1

    公开(公告)日：2024-02-29

    申请号：US18504018

    申请日：2023-11-07

    Applicant: Kioxia Corporation

    Inventor： Hideyuki KATAOKA ,  Yoshinao SUZUKI ,  Mai SHIMIZU ,  Kazuyoshi MURAOKA ,  Masami MASUDA ,  Yoshikazu HOSOMURA

    IPC: G11C11/4096 ,  G11C5/06 ,  G11C11/4072 ,  G11C11/4076

    CPC classification number: G11C11/4096 ,  G11C5/063 ,  G11C11/4072 ,  G11C11/4076

    Abstract: A semiconductor memory device comprises a first memory cell and a second memory cell. The semiconductor memory device is configured to be able to perform: a first operation which is a read operation or the like to the first memory cell; and a second operation which is a read operation or the like to the second memory cell. The semiconductor memory device transitions to a standby mode after performing the first operation in response to an input of a first command set and a second command set. The semiconductor memory device performs a charge share operation after the standby mode is released in response to an input of a third command set and a fourth command set during the standby mode. The semiconductor memory device performs the second operation using at least a part of an electric charge generated when the first operation is performed.

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