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    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    1.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20240395707A1

    公开(公告)日：2024-11-28

    申请号：US18657050

    申请日：2024-05-07

    Applicant: Kioxia Corporation

    Inventor： Hiroomi NAKAJIMA ,  Go OIKE

    IPC: H01L23/528 ,  G11C16/04 ,  H01L23/522 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

    Abstract: In one embodiment, a semiconductor device includes a first substrate. The device further includes a memory cell array including a plurality of first electrode layers that are provided above the first substrate, and are spaced from each other in a first direction, a columnar portion that is provided in the plurality of first electrode layers, extends in the first direction, and includes a charge storage layer and a semiconductor layer, and a first metal layer that is provided above the plurality of first electrode layers, and is electrically connected to an end of the semiconductor layer. The device further includes a first plug provided above the first substrate. The device further includes a first interconnect layer provided above the first plug, and electrically connected to the first plug through the first metal layer.

    SEMICONDUCTOR MEMORY
    4.
    发明申请
    SEMICONDUCTOR MEMORY 有权

    公开(公告)号：US20220302156A1

    公开(公告)日：2022-09-22

    申请号：US17835134

    申请日：2022-06-08

    Applicant: KIOXIA CORPORATION

    Inventor： Go OIKE

    IPC: H01L27/11578 ,  H01L27/11582 ,  H01L23/528 ,  H01L27/11556 ,  H01L23/522 ,  H01L27/11551 ,  H01L27/11514 ,  H01L27/1156 ,  H01L27/11521 ,  H01L27/11553 ,  H01L27/1157 ,  H01L27/06

    Abstract: A semiconductor memory includes first to fourth stacked bodies. The first stacked body includes a first conductor, and an alternating stack of first insulators and second conductors above the first conductor in a region. The second stacked body includes a third conductor, and an alternating stack of second insulators and fourth conductors above the third conductor in another region. The third stacked body includes a fifth conductor adjacent to the first conductor via a third insulator in a separation region. The fourth stacked body includes a seventh conductor adjacent to the third conductor via a fifth insulator in the separation region. The fifth conductor is electrically insulated from the seventh conductor.

    SEMICONDUCTOR STORAGE DEVICE
    5.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE 有权

    公开(公告)号：US20210384215A1

    公开(公告)日：2021-12-09

    申请号：US17407520

    申请日：2021-08-20

    Applicant: KIOXIA CORPORATION

    Inventor： Go OIKE

    IPC: H01L27/11575 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11519 ,  H01L21/768 ,  H01L27/11556 ,  H01L23/522 ,  H01L27/11548

    Abstract: A semiconductor storage device includes a base body, a stacked body, a plurality of columns, and a plurality of first contacts. The base body includes a substrate, a semiconductor element on the substrate, a lower wiring layer above the semiconductor element in a thickness direction of the base body and connected to the semiconductor element, and a lower conductive layer above the lower wiring layer in the thickness direction. The stacked body is above the lower conductive layer and including an alternating stack of conductive layers and insulating layers. Each of the columns includes a semiconductor body extending through the stacked body and electrically connected to the lower conductive layer. The plurality of first contacts extend through the stacked body and electrically connected to the lower conductive layer. The lower conductive layer is separately provided under each of the plurality of first contacts.

    SEMICONDUCTOR MEMORY DEVICE
    6.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20210091003A1

    公开(公告)日：2021-03-25

    申请号：US17018838

    申请日：2020-09-11

    Applicant: Kioxia Corporation

    Inventor： Go OIKE

    IPC: H01L23/535 ,  H01L27/11565 ,  H01L27/11582 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/528 ,  H01L21/768

    Abstract: According to one embodiment, a semiconductor memory device includes a stacked body, a pillar, a strip part, a plurality of first contacts, and a second contact. The stacked body includes a plurality of conductive layers stacked via an insulating layer, and includes, at each of opposite ends in a first direction, a first staircase part in which the conductive layers are terminated stepwise. The pillar extends in the stacked body in a stacking direction of the stacked body, and form memory cells at positions intersecting with at least some conductive layers of the plurality of conductive layers. The strip part divides the stacked body in the first direction by extending in a second direction crossing the first direction. The plurality of first contacts are arranged in the first staircase part, in which each of the first contacts is connected to one of the conductive layers at each step of the first staircase part. The second contact is arranged on the strip part side of the stacked body and is connected to an uppermost conductive layer of the plurality of conductive layers, the some conductive layers are connected to the memory cells and arranged in contact with the strip part, of the plurality of conductive layers.

    SEMICONDUCTOR MEMORY DEVICE
    10.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 有权

    公开(公告)号：US20250159891A1

    公开(公告)日：2025-05-15

    申请号：US19025928

    申请日：2025-01-16

    Applicant: KIOXIA CORPORATION

    Inventor： Go OIKE ,  Tsuyoshi SUGISAKI

    IPC: H10B43/27 ,  G11C5/06 ,  G11C16/04 ,  G11C16/08 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/35 ,  H10D30/69

    Abstract: According to one embodiment, a semiconductor memory device includes a plurality of first interconnect layers, first and second memory pillars, and a plurality of first plugs. The plurality of first interconnect layers include a first array region where the first memory pillar penetrates the plurality of first interconnect layers, a second array region where the second memory pillar penetrates the plurality of first interconnect layers, and a coupling region where a plurality of coupling parts respectively coupled to the plurality of first plugs are formed. Along a first direction parallel to the semiconductor substrate, the first array region, the coupling region, and the second array region are arranged in order.

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