公开(公告)号：US20250068354A1

公开(公告)日：2025-02-27

申请号：US18938627

申请日：2024-11-06

Applicant: Kioxia Corporation

Inventor： Hideki YOSHIDA ,  Shinichi KANNO ,  Naoki ESAKA

IPC: G06F3/06

Abstract: A controller manages a plurality of block groups each including one or more blocks among a plurality of blocks provided in a non-volatile memory. The controller assigns one of the plurality of block groups to each of plurality of zones. The controller writes write data which is to be written to a first zone to a shared write buffer and writes write data which is to be written to a second zone to the shared write buffer. When a total size of the write data in the first zone stored in the shared write buffer reaches a capacity of the first zone, the controller copies the write data in the first zone stored in the shared write buffer to the first block group assigned to the first zone.

公开(公告)号：US20250013385A1

公开(公告)日：2025-01-09

申请号：US18892722

申请日：2024-09-23

Applicant: KIOXIA CORPORATION

Inventor： Shinichi KANNO ,  Hideki YOSHIDA ,  Naoki ESAKA

IPC: G06F3/06 ,  G06F12/0804

Abstract: According to one embodiment, a memory system receives from a host a first write request including a first block identifier designating a first write destination block to which first write data is to be written. The memory system acquires the first write data from a write buffer temporarily holding write data corresponding to each of the write requests, and writes the first write data to a write destination page in the first write destination block. The memory system releases a region in the write buffer, storing data which is made readable from the first write destination block by writing the first write data to the write destination page. The data made readable is a data of a page in the first write destination block preceding the write destination page.

公开(公告)号：US20230297246A1

公开(公告)日：2023-09-21

申请号：US17939150

申请日：2022-09-07

Applicant: Kioxia Corporation

Inventor： Koichi NAGAI ,  Naoki ESAKA ,  Toyohide ISSHI

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0679 ,  G06F3/0659

Abstract: According to one embodiment, an information processing apparatus includes a nonvolatile memory and a CPU. The CPU stores, to the nonvolatile memory, first data, and management data including information equivalent to a write command associated with the first data and designating a first LBA range, and performs a first transmission of the write command to a memory system. When writing of second data to a second LBA range including a third LBA range that is at least a portion of the first LBA range or deallocation of the second LBA range is requested before a second response to the write command is received, the CPU transmits, to the system, a command to cancel writing to at least the third LBA range from writing of the first data to the first LBA range in accordance with the write command.

公开(公告)号：US20230070397A1

公开(公告)日：2023-03-09

申请号：US17653393

申请日：2022-03-03

Applicant: Kioxia Corporation

Inventor： Naoki ESAKA ,  Koichi NAGAI ,  Toyohide ISSHI

IPC: G06F3/06

Abstract: According to one embodiment, an information processing apparatus includes a nonvolatile memory and a CPU. The CPU stores first data in the nonvolatile memory, performs a first transmission of a write request associated with the first data to the memory system, and stores management data including information equivalent to the write request in the nonvolatile memory. In response to receiving a first response to the write request transmitted in the first transmission, the CPU adds, to the management data, information indicating that the first response has been received. The CPU deletes the first data and the management data in response to receiving a second response to the write request transmitted in the first transmission after receiving the first response.

公开(公告)号：US20220300182A1

公开(公告)日：2022-09-22

申请号：US17468163

申请日：2021-09-07

Applicant: Kioxia Corporation

Inventor： Naoki ESAKA ,  Shinichi KANNO

IPC: G06F3/06

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller receives a first write request associated with first data from a host. In response to a lapse of first time since the reception of the first write request, the controller starts a write process of second data to the nonvolatile memory. The second data includes at least the first data. The controller transmits a first response to the first write request to the host in response to completion of the write process. The first time is time obtained by subtracting second time from third time designated by the host as a time limit of the transmission of the first response since the reception of the first write request.

公开(公告)号：US20230376239A1

公开(公告)日：2023-11-23

申请号：US18365617

申请日：2023-08-04

Applicant: Kioxia Corporation

Inventor： Hideki YOSHIDA ,  Shinichi KANNO ,  Naoki ESAKA

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0679 ,  G06F3/0604

Abstract: A controller manages a plurality of block groups each including one or more blocks among a plurality of blocks provided in a non-volatile memory. The controller assigns one of the plurality of block groups to each of plurality of zones. The controller writes write data which is to be written to a first zone to a shared write buffer and writes write data which is to be written to a second zone to the shared write buffer. When a total size of the write data in the first zone stored in the shared write buffer reaches a capacity of the first zone, the controller copies the write data in the first zone stored in the shared write buffer to the first block group assigned to the first zone.

公开(公告)号：US20220236916A1

公开(公告)日：2022-07-28

申请号：US17473634

申请日：2021-09-13

Applicant: Kioxia Corporation

Inventor： Naoki ESAKA ,  Shinichi KANNO

IPC: G06F3/06

Abstract: According to one embodiment, in response to receiving a first namespace create command specifying a first attribution from a host, a controller creates a first namespace having the first attribution and a first logical address range. The first logical address range includes logical addresses. The controller sets each of the logical addresses to an unallocated state in which a physical address of the nonvolatile memory is not mapped, during a first period from a time when receiving a power loss advance notification or when detecting an unexpected power loss until a time when the controller becomes a ready state by resupply of a power to the memory system.

公开(公告)号：US20220188005A1

公开(公告)日：2022-06-16

申请号：US17468880

申请日：2021-09-08

Applicant: Kioxia Corporation

Inventor： Naoki ESAKA

IPC: G06F3/06

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The controller manages at least one storage area that is obtained by logically dividing a storage space of the nonvolatile memory. One or more storage areas in the at least one storage area store one or more data pieces, respectively. The controller manages first information on one or more times in which integrity of the one or more data pieces have been confirmed last, respectively.

公开(公告)号：US20220083234A1

公开(公告)日：2022-03-17

申请号：US17536558

申请日：2021-11-29

Applicant: Kioxia Corporation

Inventor： Naoki ESAKA ,  Shinichi KANNO

IPC: G06F3/06

Abstract: According to one embodiment, a controller of a memory system performs a first operation a plurality of times for each of a plurality of first blocks. The first operation includes a write operation for writing data in a first write mode for writing m-bit data per memory cell and a data erase operation. While a second block is not a defective block, the controller performs a second operation a plurality of times for the second block. The second operation includes a write operation for writing data in a second write mode for writing n-bit data per memory cell and a data erase operation. When the second block is a defective block, the controller selects a first block from the plurality of first blocks, and writes second write data to the selected first block in the second write mode.

公开(公告)号：US20240427941A1

公开(公告)日：2024-12-26

申请号：US18822835

申请日：2024-09-03

Applicant: Kioxia Corporation

Inventor： Naoki ESAKA ,  Yoshiyuki KUDOH

IPC: G06F21/64 ,  G06F21/79

Abstract: According to one embodiment, a memory system includes a nonvolatile memory and a controller. The nonvolatile memory includes storage areas each configured to store user data. The controller acquires first information related to the number of program/erase cycles for at least one of the storage areas. In response to acquisition of the first information, the controller executes a data erase operation on each of the storage areas. In response to completion of the data erase operation, the controller acquires second information related to the number of program/erase cycles for the at least one of the storage areas. The controller generates an erase certificate that includes the first information and the second information.