公开(公告)号：US12136458B2

公开(公告)日：2024-11-05

申请号：US17897089

申请日：2022-08-26

Applicant: KIOXIA CORPORATION

Inventor： Tomoki Nakagawa ,  Koji Kato ,  Shuhei Oketa ,  Mai Shimizu

IPC: G11C7/10 ,  G11C16/04 ,  G11C16/08

Abstract: A semiconductor memory device includes a memory string, a voltage supply circuit, a plurality of control signal lines, a row decoder, and a control circuit. The voltage supply circuit is configured to generate a plurality of operation voltages to operate the semiconductor memory device. The operation voltages include a negative voltage. The plurality of control signal lines is connected between the voltage supply circuit and the memory string. The row decoder includes a plurality of transistors provided in the plurality of control signal lines, respectively. The control circuit is configured to control the transistors of the row decoder, and cause the negative voltage to be supplied to the row decoder during a certain period of time in which a voltage of one of the control signal lines drops to a negative level.