公开(公告)号：US20220308772A1

公开(公告)日：2022-09-29

申请号：US17465501

申请日：2021-09-02

Applicant: KIOXIA CORPORATION

Inventor： Shinji YONEZAWA ,  Tomoyuki KANTANI

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/10 ,  G11C16/08 ,  G11C16/26

Abstract: According to one embodiment, a memory system includes first and second memory chips. The first memory chip has a first plane with a first block and a second block and a second plane with a third block and a fourth block. The second memory chip has a third plane with a fifth block and a sixth block and a fourth plane with a seventh block and an eighth block. The memory controller sets the first and third blocks as a first block unit in a user data storage area and the fifth and seventh blocks as a second block unit in the user data storage area. The memory controller allocates the second block, the fourth block, the sixth block, and the eighth block to a management data storage area. The memory controller manages user data operations for accessing the user data storage area in block units.

公开(公告)号：US20240094932A1

公开(公告)日：2024-03-21

申请号：US18176452

申请日：2023-02-28

Applicant: Kioxia Corporation

Inventor： Tomoyuki KANTANI ,  Kousuke FUJITA ,  Iku ENDO

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F3/0607 ,  G06F3/0659 ,  G06F3/0679

Abstract: A memory system includes a memory controller configured to write data in a first mode to a first block of a first area of a non-volatile memory. The first mode is a write mode for writing data with a first number of bits per memory cell. The memory controller is further configured to execute copy processing on the data written in the first mode to the first block, by writing system data written in the first block to a second block of the first area in the first mode and writing user data written in the first block to a third block of a second area of the non-volatile memory in the second mode. The second mode is a write mode for writing data with a second number of bits larger than the first number of bits per memory cell.

公开(公告)号：US20230289067A1

公开(公告)日：2023-09-14

申请号：US17821960

申请日：2022-08-24

Applicant: Kioxia Corporation

Inventor： Tomoyuki KANTANI

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0679 ,  G06F3/0629

Abstract: According to one embodiment, a controller identifies a fourth storage location on which a second step program operation is executed last among storage locations of a block and determines whether a condition that a fifth storage location stores unreadable data and each of memory cells of a sixth storage location has a threshold voltage corresponding to an erased state, is satisfied. Among the storage locations, in response to completion of a first step program operation on the fifth storage location, the second step program operation on the fourth storage location has been executed, and the first step program operation on the sixth storage location is to be executed after completion of the second step program operation on the fifth storage location.

公开(公告)号：US20240393971A1

公开(公告)日：2024-11-28

申请号：US18797068

申请日：2024-08-07

Applicant: Kioxia Corporation

Inventor： Tomoyuki KANTANI ,  Kousuke FUJITA ,  Iku ENDO

IPC: G06F3/06

Abstract: A memory system includes a non-volatile memory and a memory controller. The memory controller is configured to perform a write operation on the non-volatile memory in response to a write command from a host by writing system data in a first mode to a first block of the non-volatile memory, the first mode being a write mode for writing data with a first number of bits per memory cell, writing user data in the first mode to a second block of the non-volatile memory when the write command is of a first type, and writing user data in a second mode to a third block of the non-volatile memory when the write command is of a second type. The second mode is a write mode for writing data with a second number of bits larger than the first number of bits per memory cell.

公开(公告)号：US20240338129A1

公开(公告)日：2024-10-10

申请号：US18746394

申请日：2024-06-18

Applicant: Kioxia Corporation

Inventor： Tomoyuki KANTANI

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0679

Abstract: According to one embodiment, a controller identifies a fourth storage location on which a second step program operation is executed last among storage locations of a block and determines whether a condition that a fifth storage location stores unreadable data and each of memory cells of a sixth storage location has a threshold voltage corresponding to an erased state, is satisfied. Among the storage locations, in response to completion of a first step program operation on the fifth storage location, the second step program operation on the fourth storage location has been executed, and the first step program operation on the sixth storage location is to be executed after completion of the second step program operation on the fifth storage location.