公开(公告)号：US20220285934A1

公开(公告)日：2022-09-08

申请号：US17474941

申请日：2021-09-14

Applicant: Kioxia Corporation

Inventor： Shigefumi ISHIGURO ,  Yasuhiro SUEMATSU ,  Takeshi MIYABA ,  Kimimasa IMAI ,  Maya INAGAKI

IPC: H02H9/04 ,  H03K19/20 ,  H03H7/01

Abstract: In one embodiment, a protection circuit in a semiconductor device includes first and second transistors including gates electrically connected to a first node, and connected in series to each other between the first and second lines, third and fourth transistors including gates electrically connected to a second node between the first and second transistors, and connected in series to each other between the first and second lines, and a fifth transistor including a gate electrically connected to a third node between the third and fourth transistors, and provided between the second node and the second line. The protection circuit further includes an arithmetic circuit configured to perform calculation using a first signal received from the second node to output a second signal, and a sixth transistor configured to receive the second signal to output a control signal to the arithmetic circuit.

公开(公告)号：US20220285337A1

公开(公告)日：2022-09-08

申请号：US17350852

申请日：2021-06-17

Applicant: Kioxia Corporation

Inventor： Yasuhiro SUEMATSU ,  Maya INAGAKI

IPC: H01L27/02 ,  H01L29/417 ,  H01L23/522 ,  H01L27/11582 ,  H01L27/11573

Abstract: In one embodiment, a semiconductor device includes substrate, a plurality of electrode layers provided above the substrate, and separated from each other in a first direction perpendicular to a surface of the substrate, and a first plug provided in the plurality of electrode layers. The device further includes first and second diffusion layers provided in the substrate, one of the first and second diffusion layers functioning as an anode layer of an ESD (electrostatic discharge) protection circuit, the other of the first and second diffusion layers functioning as a cathode layer of the ESD protection circuit, a second plug provided at a position that overlaps with the first diffusion layer in planar view, and electrically connected with the first diffusion layer, and a third plug provided at a position that does not overlap with the first diffusion layer in planar view, and electrically connected with the first diffusion layer.

公开(公告)号：US20210082525A1

公开(公告)日：2021-03-18

申请号：US16807890

申请日：2020-03-03

Applicant: KIOXIA CORPORATION

Inventor： Yasuhiro SUEMATSU ,  Masaru KOYANAGI ,  Kensuke YAMAMOTO ,  Ryo FUKUDA

IPC: G11C16/30 ,  G11C16/26 ,  G11C16/10

Abstract: A semiconductor device includes pads for inputting and outputting data, a plurality of control circuit groups connected to the pads, a first supply line for supplying a first electric potential to the control circuit groups, and a second supply line for supplying a second electric potential lower than the first electric potential to the control circuit groups. At least one of the first electric potential supply line or the second supply line is provided with a blocking region such that the blocking region prevents supply of the first electric potential, and the first electric potential is supplied to the plurality of control circuit groups from the first supply line divided by the blocking region, or the blocking region prevents supply of the second electric potential, and the second electric potential is supplied to the plurality of control circuit groups from the second supply line divided by the blocking region.

公开(公告)号：US20240313527A1

公开(公告)日：2024-09-19

申请号：US18584301

申请日：2024-02-22

Applicant: Kioxia Corporation

Inventor： Shigefumi ISHIGURO ,  Yasuhiro SUEMATSU ,  Masaru KOYANAGI ,  Maya INAGAKI ,  Kentaro WATANABE ,  Shoki ITO

IPC: H02H9/04

CPC classification number: H02H9/046

Abstract: A semiconductor device includes a protection circuit electrically connected to a first interconnection and a second interconnection, a first voltage and a second voltage supplied to the first interconnection and the second interconnection, respectively. The protection circuit includes: a first resistor connected between the first interconnection and a first node; a first capacitor connected between the second interconnection and the first node; a second resistor connected between the second interconnection and a second node located; a second capacitor connected between the second interconnection and the second node, and connected in parallel to the second resistor; a third resistor connected between the first interconnection and a third node; and a third capacitor connected between the second interconnection and the third node.