公开(公告)号：US20230223938A1

公开(公告)日：2023-07-13

申请号：US18125081

申请日：2023-03-22

Applicant: Kioxia Corporation

Inventor： Junya MATSUNO ,  Kensuke YAMAMOTO ,  Ryo FUKUDA ,  Masaru KOYANAGI ,  Kenro KUBOTA ,  Masato DOME

IPC: G11C7/10

CPC classification number: G11C7/1048

Abstract: A device includes a memory cell array configured to store data; and a signal propagation circuit configured to propagate a signal between the memory cell array and a host. The signal propagation circuit includes a first inverted signal output circuit, a second inverted signal output circuit including an input terminal connected to i) an output terminal of the first inverted signal output circuit and ii) an output terminal of the second inverted signal output circuit, a third inverted signal output circuit including an input terminal connected to i) the output terminal of the first inverted signal output circuit and ii) the output terminal of the second inverted signal output circuit, and a fourth inverted signal output circuit including an input terminal connected to i) an output terminal of the third inverted signal output circuit and ii) an output terminal of the fourth inverted signal output circuit.

公开(公告)号：US20240312532A1

公开(公告)日：2024-09-19

申请号：US18672202

申请日：2024-05-23

Applicant: Kioxia Corporation

Inventor： Junya MATSUNO ,  Kenro KUBOTA ,  Masato DOME ,  Kensuke YAMAMOTO ,  Kei SHIRAISHI ,  Kazuhiko SATOU ,  Ryo FUKUDA ,  Masaru KOYANAGI

IPC: G11C16/32 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  H10B69/00

CPC classification number: G11C16/32 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  H10B69/00

Abstract: A semiconductor memory device includes a memory cell array having a memory cell; a data signal terminal configured to receive data to be written into the memory cell from an exterior of the semiconductor memory device and to output data read from the memory cell to the exterior of the semiconductor memory, and a timing signal terminal configured to receive a timing control signal. An interface circuit includes a first comparator having a first input terminal connected to the data signal terminal, a second input terminal connected to a reference voltage, and an output terminal. A plurality of first inverters are connected in series, an input terminal of a first stage one of the first inverters being connected to the output terminal first of the first comparator. A first switch circuit has a first terminal connected to an output terminal of a final stage one of the first inverters and a second terminal; a second inverter having an input terminal connected to the second terminal of the first switch and an output terminal connected to the second terminal of the first switch; and a first latch circuit connected to the second terminal of the first switch.

公开(公告)号：US20230028971A1

公开(公告)日：2023-01-26

申请号：US17959098

申请日：2022-10-03

Applicant: Kioxia Corporation

Inventor： Masato DOME ,  Kensuke YAMAMOTO ,  Masaru KOYANAGI ,  Ryo FUKUDA ,  Junya MATSUNO ,  Kenro KUBOTA

IPC: G11C16/30 ,  G11C16/04

Abstract: According to one embodiment, a semiconductor memory device includes: first and second circuit units, a driver circuit, an input/output pad, first and second power supply pads, and first and second interconnects. The first interconnect is configured to provide coupling between the first circuit unit and the first power supply pad. The second interconnect is configured to provide coupling between the second circuit unit and the first power supply pad and have no electrical coupling to the first interconnect.

公开(公告)号：US20220093185A1

公开(公告)日：2022-03-24

申请号：US17202590

申请日：2021-03-16

Applicant: Kioxia Corporation

Inventor： Masato DOME ,  Kensuke YAMAMOTO ,  Masaru KOYANAGI ,  Ryo FUKUDA ,  Junya MATSUNO ,  Kenro KUBOTA

IPC: G11C16/30 ,  G11C16/04

Abstract: According to one embodiment, a semiconductor memory device includes: first and second circuit units, a driver circuit, an input/output pad, first and second power supply pads, and first and second interconnects. The first interconnect is configured to provide coupling between the first circuit unit and the first power supply pad. The second interconnect is configured to provide coupling between the second circuit unit and the first power supply pad and have no electrical coupling to the first interconnect.

公开(公告)号：US20210226632A1

公开(公告)日：2021-07-22

申请号：US17002816

申请日：2020-08-26

Applicant: Kioxia Corporation

Inventor： Junya MATSUNO ,  Kensuke YAMAMOTO ,  Ryo FUKUDA ,  Masaru KOYANAGI ,  Kenro KUBOTA ,  Masato DOME

IPC: H03K19/0185 ,  G11C7/10

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell array and a signal propagation circuit disposed on a propagation path of a signal or a control signal, wherein the signal propagation circuit includes: a first inverted signal output circuit; a second inverted signal output circuit including an input terminal connected to an output terminal of the first inverted signal output circuit; a third inverted signal output circuit including an input terminal connected to output terminals of the first inverted signal output circuit and the second inverted signal output circuit; a fourth inverted signal output circuit including an input terminal connected to an output terminal of the third inverted signal output circuit; and a fifth inverted signal output circuit including an input terminal connected to output terminals of the third inverted signal output circuit and the fourth inverted signal output circuit.

公开(公告)号：US20220093188A1

公开(公告)日：2022-03-24

申请号：US17202661

申请日：2021-03-16

Applicant: Kioxia Corporation

Inventor： Junya MATSUNO ,  Kenro KUBOTA ,  Masato DOME ,  Kensuke YAMAMOTO ,  Kei SHIRAISHI ,  Kazuhiko SATOU ,  Ryo FUKUDA ,  Masaru KOYANAGI

IPC: G11C16/32 ,  G11C16/04

Abstract: According to an embodiment, a semiconductor device includes a first circuit, a second circuit, and a third circuit. The first circuit is configured to receive a first signal, and output a first voltage to a first node in accordance with a voltage of the first signal being at a first level and output a second voltage to the first node in accordance with the voltage of the first signal being at a second level. The first voltage is higher than the second voltage. The second circuit is coupled to the first node and configured to latch data based on a voltage of the first node. The third circuit includes a first inverter. The first inverter includes a first input terminal coupled to the first node and a first output terminal coupled to the first node.

公开(公告)号：US20220059165A1

公开(公告)日：2022-02-24

申请号：US17329317

申请日：2021-05-25

Applicant: Kioxia Corporation

Inventor： Kazuhiko SATOU ,  Ryo FUKUDA ,  Masaru KOYANAGI ,  Kensuke YAMAMOTO ,  Masato DOME ,  Kei SHIRAISHI ,  Junya MATSUNO ,  Kenro KUBOTA

IPC: G11C16/04 ,  H03K19/20 ,  H03K19/00 ,  G11C16/26

Abstract: A semiconductor storage device including an output pad, a first circuit connected to the output pad, a second circuit connected to the first circuit, a third circuit configured to output a first setting signal for controlling the first circuit accordance with a characteristic variation of the first circuit, and a fourth circuit configured to generate a second setting signal for controlling the second circuit in accordance with the first setting signal received from the third circuit and output the second setting signal to the second circuit.

公开(公告)号：US20210271615A1

公开(公告)日：2021-09-02

申请号：US16999121

申请日：2020-08-21

Applicant: Kioxia Corporation

Inventor： Kensuke YAMAMOTO ,  Masaru KOYANAGI ,  Ryo FUKUDA ,  Junya MATSUNO ,  Kenro KUBOTA ,  Masato DOME

IPC: G06F13/16

Abstract: A non-volatile semiconductor memory device including: a first pad transmitting/receiving a data signal transmitted via a first signal line to/from a memory controller; a second pad transmitting/receiving a strobe signal transmitted via a second signal line to/from the memory controller, the strobe signal specifying a timing of transmitting/receiving the data signal; and a third pad receiving an output instruction signal via a third signal line from the memory controller, the output instruction signal instructing a transmission of the data signal; wherein the non-volatile semiconductor memory device outputs the data signal from the first pad to the memory controller, outputs the strobe signal from the second pad to the memory controller, performs a first calibration operation calibrating the data signal, and performs a second calibration operation calibrating the strobe signal, based on a toggle timing of the strobe signal associated with the output instruction signal.

公开(公告)号：US20210082525A1

公开(公告)日：2021-03-18

申请号：US16807890

申请日：2020-03-03

Applicant: KIOXIA CORPORATION

Inventor： Yasuhiro SUEMATSU ,  Masaru KOYANAGI ,  Kensuke YAMAMOTO ,  Ryo FUKUDA

IPC: G11C16/30 ,  G11C16/26 ,  G11C16/10

Abstract: A semiconductor device includes pads for inputting and outputting data, a plurality of control circuit groups connected to the pads, a first supply line for supplying a first electric potential to the control circuit groups, and a second supply line for supplying a second electric potential lower than the first electric potential to the control circuit groups. At least one of the first electric potential supply line or the second supply line is provided with a blocking region such that the blocking region prevents supply of the first electric potential, and the first electric potential is supplied to the plurality of control circuit groups from the first supply line divided by the blocking region, or the blocking region prevents supply of the second electric potential, and the second electric potential is supplied to the plurality of control circuit groups from the second supply line divided by the blocking region.

公开(公告)号：US20230018613A1

公开(公告)日：2023-01-19

申请号：US17952659

申请日：2022-09-26

Applicant: Kioxia Corporation

Inventor： Junya MATSUNO ,  Kenro KUBOTA ,  Masato DOME ,  Kensuke YAMAMOTO ,  Kei SHIRAISHI ,  Kazuhiko SATOU ,  Ryo FUKUDA ,  Masaru KOYANAGI

IPC: G11C16/32 ,  G11C16/04

Abstract: A semiconductor device includes a first circuit configured to receive a first signal, and output a first voltage to a first node in accordance with a voltage of the first signal being at a first level and output a second voltage to the first node in accordance with the voltage of the first signal being at a second level, the first voltage being higher than the second voltage. A second circuit is coupled to the first node and is configured to latch data based on a voltage of the first node; and a third circuit is coupled to the first node and is configured to output a third voltage to the first node while the first circuit is outputting the first voltage to the first node, and to output a fourth voltage to the first node while the first circuit is outputting the second voltage to the first node, the third voltage being lower than the first voltage, and the fourth voltage being higher than the second voltage.