公开(公告)号：US20220059570A1

公开(公告)日：2022-02-24

申请号：US17189197

申请日：2021-03-01

Applicant: KIOXIA CORPORATION

Inventor： Yusuke TANAKA ,  Masumi SAITOH ,  Kensuke OTA

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L29/24 ,  H01L29/51

Abstract: According to one embodiment, a semiconductor memory device includes a ferroelectric layer and a first semiconductor layer. The first semiconductor layer is electrically connected to a first electrode and a second electrode and includes an n-type oxide semiconductor. A third electrode is opposite the first semiconductor layer. The ferroelectric layer is between the third electrode and the first semiconductor layer. A second semiconductor layer includes at least one of a Group IV semiconductor material or a p-type oxide semiconductor material. The first semiconductor layer is between the ferroelectric layer and the second semiconductor layer.