公开(公告)号：US20220013529A1

公开(公告)日：2022-01-13

申请号：US17198688

申请日：2021-03-11

Applicant: Kioxia Corporation

Inventor： Daisuke MATSUBAYASHI ,  Masumi SAITOH

IPC: H01L27/115

Abstract: A storage device of an embodiment includes a first conductive layer; a second conductive layer; a fluid layer between the first conductive layer and the second conductive layer; particles in the fluid layer; a first control electrode between the first conductive layer and the second conductive layer; a first insulating layer between the first conductive layer and the first control electrode surrounding the fluid layer; and a second insulating layer between the first control electrode and the second conductive layer surrounding the fluid layer. In this storage device, a first cross-sectional area of the fluid layer in a first cross-section perpendicular to a first direction is smaller than a second cross-sectional area of the fluid layer in a second cross-section perpendicular to the first direction. The first cross-section includes the first control electrode, and the second cross-section includes the second insulating layer.

公开(公告)号：US20210082956A1

公开(公告)日：2021-03-18

申请号：US16894986

申请日：2020-06-08

Applicant: Kioxia Corporation

Inventor： Kunifumi SUZUKI ,  Masumi SAITOH

IPC: H01L27/11597 ,  H01L27/11587

Abstract: Provided is a semiconductor memory device according to an embodiment including: a stacked body including gate electrode layers stacked in a first direction; a semiconductor layer provided in the stacked body and extending in the first direction; and a gate insulating layer provided between the semiconductor layer and at least one of the gate electrode layers, and the gate insulating layer including a first region containing a first oxide including at least one of a hafnium oxide and a zirconium oxide, in which a first length of the at least one of the gate electrode layers in the first direction is larger than a second length of the first region in the first direction.

公开(公告)号：US20230074030A1

公开(公告)日：2023-03-09

申请号：US17984959

申请日：2022-11-10

Applicant: KIOXIA CORPORATION

Inventor： Hiroshi MAEJIMA ,  Toshifumi HASHIMOTO ,  Takashi MAEDA ,  Masumi SAITOH ,  Tetsuaki UTSUMI

IPC: H01L25/065 ,  H01L25/18 ,  H01L23/00

Abstract: A semiconductor memory device includes a memory chip. The memory chip includes a first region including a plurality of first memory cells and second memory cells, a second region different from the first region, a plurality of first word lines stacked apart from each other in a first direction in the first and second regions, a first pillar including a first semiconductor layer extending through the first word lines, and a first insulator layer provided between the first semiconductor layer and the first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines, a first bonding pad in the second region, and a first transistor between the first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region.

公开(公告)号：US20220406796A1

公开(公告)日：2022-12-22

申请号：US17645133

申请日：2021-12-20

Applicant: Kioxia Corporation

Inventor： Harumi SEKI ,  Kensuke OTA ,  Masumi SAITOH

IPC: H01L27/1159 ,  H01L27/11597 ,  H01L29/51

Abstract: A semiconductor memory device according to an embodiment includes: a semiconductor layer extending in a first direction; a first gate electrode layer; a first insulating layer between the semiconductor layer and the first gate electrode layer; a second insulating layer between the first insulating layer and the first gate electrode layer, the second insulating layer having a first portion containing a ferroelectric material; and a first layer between the first insulating layer and the second insulating layer, the first layer containing silicon, nitrogen, and fluorine, the first layer having a first region and a second region between the first region and the second insulating layer, the first layer having a second atomic ratio of nitrogen to silicon in the second region higher than a first atomic ratio of nitrogen to silicon in the first region, and the first layer having fluorine concentration higher than the second region.

公开(公告)号：US20220310170A1

公开(公告)日：2022-09-29

申请号：US17447594

申请日：2021-09-14

Applicant: Kioxia Corporation

Inventor： Reika TANAKA ,  Masumi SAITOH

IPC: G11C16/14 ,  G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C5/06

Abstract: A semiconductor memory device includes a semiconductor layer, a gate electrode, a gate insulating film disposed therebetween, first and second wirings connected to the semiconductor layer, and a third wiring connected to the gate electrode and is configured to execute a write operation, an erase operation, and a read operation. In the write operation, a write voltage of a first polarity is supplied between the third wiring and at least one of the first wiring or the second wiring. In the erase operation, an erase voltage of a second polarity is supplied between the third wiring and at least one of the first wiring or the second wiring. In the read operation, the write voltage or a voltage having a larger amplitude than that of the write voltage is supplied between the third wiring and at least one of the first wiring or the second wiring.

公开(公告)号：US20220059570A1

公开(公告)日：2022-02-24

申请号：US17189197

申请日：2021-03-01

Applicant: KIOXIA CORPORATION

Inventor： Yusuke TANAKA ,  Masumi SAITOH ,  Kensuke OTA

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L29/24 ,  H01L29/51

Abstract: According to one embodiment, a semiconductor memory device includes a ferroelectric layer and a first semiconductor layer. The first semiconductor layer is electrically connected to a first electrode and a second electrode and includes an n-type oxide semiconductor. A third electrode is opposite the first semiconductor layer. The ferroelectric layer is between the third electrode and the first semiconductor layer. A second semiconductor layer includes at least one of a Group IV semiconductor material or a p-type oxide semiconductor material. The first semiconductor layer is between the ferroelectric layer and the second semiconductor layer.

公开(公告)号：US20240274207A1

公开(公告)日：2024-08-15

申请号：US18437664

申请日：2024-02-09

Applicant: Kioxia Corporation

Inventor： Reika TANAKA ,  Masumi SAITOH

IPC: G11C16/16 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24

CPC classification number: G11C16/16 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24

Abstract: According to one embodiment, a device includes: first and third transistors coupled to a bit line; first cells coupled to the first transistor; second cells coupled to the third transistor; a first line coupled to a gate of the first transistor; a second line coupled to a gate of the third transistor; word lines coupled to gates of the first and second cells; and a circuit. Each of the first and second cells includes a ferroelectric transistor. In the erase sequence, the circuit applies a first voltage having a positive value to the bit line, applies a second voltage higher than the first voltage to the first and second lines, applies a third voltage higher than the first voltage to non-selected word lines, and applies a fourth voltage lower than the first voltage to a selected word line.

公开(公告)号：US20220302169A1

公开(公告)日：2022-09-22

申请号：US17411733

申请日：2021-08-25

Applicant: KIOXIA CORPORATION

Inventor： Keisuke TAKAGI ,  Kazuhiro MATSUO ,  Kunifumi SUZUKI ,  Yuuichi KAMIMUTA ,  Taro SHIOKAWA ,  Masumi SAITOH ,  Yuta KAMIYA ,  Kota TAKAHASHI

IPC: H01L27/11597 ,  G11C16/04 ,  H01L27/1157 ,  H01L27/11582

Abstract: A semiconductor storage device includes a channel layer extending along a first direction and including titanium oxide, an electrode layer extending along a second direction crossing the first direction, and a ferroelectric layer between the channel layer and the electrode layer and including titanium.

公开(公告)号：US20240298450A1

公开(公告)日：2024-09-05

申请号：US18588621

申请日：2024-02-27

Applicant: Kioxia Corporation

Inventor： Haruka SAKUMA ,  Masumi SAITOH ,  Kouji MATSUO

IPC: H10B53/20 ,  H01L21/28 ,  H01L23/528 ,  H01L29/51 ,  H10B53/10

CPC classification number: H10B53/20 ,  H01L23/5283 ,  H01L29/40111 ,  H01L29/517 ,  H10B53/10

Abstract: A memory device includes: a first electrode layer extending in a first direction intersecting a surface of a substrate; a second electrode layer extending in the first direction; a first conductive layer surrounding the first electrode layer and the second electrode layer; a first insulating layer between the first electrode layer and the first conductive layer, surrounding the first electrode layer, and including hafnium oxide and/or zirconium oxide; a second insulating layer between the second electrode layer and the first conductive layer, surrounding the second electrode layer, and including hafnium oxide and/or zirconium oxide; a first gate electrode layer extending in the first direction, a first semiconductor layer surrounding the first gate electrode layer and electrically connected to the first conductive layer; and a first gate insulating layer between the first gate electrode layer and the first semiconductor layer and surrounding the first gate electrode layer.

公开(公告)号：US20220262422A1

公开(公告)日：2022-08-18

申请号：US17470802

申请日：2021-09-09

Applicant: Kioxia Corporation

Inventor： Marina YAMAGUCHI ,  Kensuke OTA ,  Kazuhiko YAMAMOTO ,  Masumi SAITOH

IPC: G11C11/22

Abstract: A memory device according to an embodiment includes first and second interconnects, memory cells, and a control circuit. In a first process, the control circuit applies a write voltage of a first direction to a memory cell coupled to selected first and second interconnects, and applies a write voltage of a second direction to a memory cell coupled to the selected first interconnect and a non-selected second interconnect. In second processes of first to m-th trial processes, the control circuit applies the write voltage of the second direction to the memory cell coupled to the selected first and second interconnects, and omits a write operation in which the memory cell coupled to the selected first interconnect and the non-selected second interconnect is targeted.