公开(公告)号：US11450390B2

公开(公告)日：2022-09-20

申请号：US17118703

申请日：2020-12-11

Applicant: Kioxia Corporation

Inventor： Fumiya Watanabe ,  Masaru Koyanagi ,  Yutaka Shimizu ,  Yasuhiro Hirashima ,  Kei Shiraishi ,  Mikihiko Ito

IPC: G11C11/08 ,  G11C16/32 ,  G11C7/10 ,  G11C16/10

Abstract: In a semiconductor integrated circuit, an input circuit includes an input and an output stage electrically connected to the input stage via a first node and a second node. The input stage includes a first transistor, a second transistor, a third transistor, a fourth transistor, a first time constant adjusting circuit, and a second time constant adjusting circuit. The first transistor includes a gate that receives an input signal. The second transistor includes a gate that receives a reference signal. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The first time constant adjusting circuit is electrically connected between a gate of the third transistor and the first node. The second time constant adjusting circuit is electrically connected between a gate of the fourth transistor and the second node.

公开(公告)号：US11456023B2

公开(公告)日：2022-09-27

申请号：US17121231

申请日：2020-12-14

Applicant: Kioxia Corporation

Inventor： Yutaka Shimizu ,  Satoshi Inoue ,  Isao Fujisawa ,  Yumi Takada

IPC: G11C11/08 ,  G11C7/10

Abstract: There is provided a semiconductor integrated circuit including an input circuit. The input circuit includes a first amplifier and a second amplifier. The second amplifier is electrically connected to the first amplifier. The second amplifier includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a time constant providing circuit. The first transistor has a gate electrically connected to a first node of the first amplifier. The second transistor has a gate electrically connected to a second node of the first amplifier. The third transistor is disposed adjacent to a drain of the first transistor. The fourth transistor is disposed adjacent to a drain of the second transistor. The time constant providing circuit is electrically connected between a gate of the third transistor and a drain of the third transistor, a gate of the fourth transistor.

公开(公告)号：US11100975B2

公开(公告)日：2021-08-24

申请号：US16803260

申请日：2020-02-27

Applicant: KIOXIA CORPORATION

Inventor： Rui Ito ,  Makoto Morimoto ,  Yutaka Shimizu ,  Ryuichi Fujimoto

IPC: G11C16/34 ,  G11C11/4074 ,  G11C11/408 ,  G11C7/10 ,  G11C11/4076 ,  G11C16/04 ,  G11C16/26

Abstract: According to one embodiment, a semiconductor memory device includes a plurality of memory cells connected to a word line, a circuit configured to apply a voltage to the word line, a detection circuit configured to detect a first time difference from when a first signal of which a voltage is increased with a first slope is applied to the word line to when a current flows through the memory cells in response to applying the first signal, and a second time difference from when a second signal of which a voltage is increased with a second slope is applied to the word line to when a current flows through the memory cells in response to applying the second signal, the second slope being different from the first slope, and a determination circuit configured to determine a threshold voltage of the memory cells based on a difference between the first time difference and the second time difference.