公开(公告)号：US20220245791A1

公开(公告)日：2022-08-04

申请号：US17722710

申请日：2022-04-18

Applicant: KLA CORPORATION

Inventor： Junqing Huang ,  Hucheng Lee ,  Sangbong Park ,  Xiaochun Li

IPC: G06T7/00 ,  H01L27/108 ,  H01L27/11556 ,  G06T7/11 ,  G01N21/95 ,  G01N21/956 ,  H01L27/11582

Abstract: With the disclosed systems and methods for DRAM and 3D NAND inspection, an image of the wafer is received based on the output for an inspection tool. Geometric measurements of a design of a plurality of memory devices on the wafer are received. A care area with higher inspection sensitivity is determined based on the geometric measurements.

公开(公告)号：US10923317B2

公开(公告)日：2021-02-16

申请号：US16543596

申请日：2019-08-18

Applicant: KLA Corporation ,  Shan Zhu

Inventor： Junqing Huang ,  Paul Russell ,  Hucheng Lee ,  Kenong Wu

IPC: H01J37/28 ,  G01N21/95 ,  H01J37/244

Abstract: Methods and systems for detecting defects in a logic region on a wafer are provided. One method includes acquiring information for different types of design-based care areas in a logic region of a wafer. The method also includes designating the different types of the design-based care areas as different types of sub-regions and, for a localized area within the logic region, assigning two or more instances of the sub-regions located in the localized area to a super-region. In addition, the method includes generating one scatter plot for all of the two or more instances of the sub-regions assigned to the super-region. The one scatter plot is generated with different segmentation values for the output corresponding to the different types of the sub-regions. The method further includes detecting defects in the sub-regions based on the one scatter plot.

公开(公告)号：US11783470B2

公开(公告)日：2023-10-10

申请号：US17722710

申请日：2022-04-18

Applicant: KLA CORPORATION

Inventor： Junqing Huang ,  Hucheng Lee ,  Sangbong Park ,  Xiaochun Li

IPC: G06K9/00 ,  G06T7/00 ,  G06T7/11 ,  G01N21/95 ,  G01N21/956 ,  H10B12/00 ,  H10B41/27 ,  H10B43/27

CPC classification number: G06T7/0006 ,  G01N21/9501 ,  G01N21/956 ,  G06T7/11 ,  H10B12/01 ,  H10B41/27 ,  H10B43/27 ,  G06T2207/30148

Abstract: With the disclosed systems and methods for DRAM and 3D NAND inspection, an image of the wafer is received based on the output for an inspection tool. Geometric measurements of a design of a plurality of memory devices on the wafer are received. A care area with higher inspection sensitivity is determined based on the geometric measurements.

公开(公告)号：US20210049755A1

公开(公告)日：2021-02-18

申请号：US16542376

申请日：2019-08-16

Applicant: KLA CORPORATION

Inventor： Junqing Huang ,  Hucheng Lee ,  Sangbong Park ,  Xiaochun Li

IPC: G06T7/00 ,  H01L27/108 ,  H01L27/11556 ,  H01L27/11582 ,  G06T7/11 ,  G01N21/95 ,  G01N21/956

Abstract: With the disclosed systems and methods for DRAM and 3D NAND inspection, an image of the wafer is received based on the output for an inspection tool. Geometric measurements of a design of a plurality of memory devices on the wafer are received. A care area with higher inspection sensitivity is determined based on the geometric measurements.

公开(公告)号：US20200090904A1

公开(公告)日：2020-03-19

申请号：US16543596

申请日：2019-08-18

Applicant: KLA Corporation

Inventor： Junqing Huang ,  Paul Russell ,  Hucheng Lee ,  Kenong Wu

IPC: H01J37/28 ,  H01J37/244 ,  G01N21/95

Abstract: Methods and systems for detecting defects in a logic region on a wafer are provided. One method includes acquiring information for different types of design-based care areas in a logic region of a wafer. The method also includes designating the different types of the design-based care areas as different types of sub-regions and, for a localized area within the logic region, assigning two or more instances of the sub-regions located in the localized area to a super-region. In addition, the method includes generating one scatter plot for all of the two or more instances of the sub-regions assigned to the super-region. The one scatter plot is generated with different segmentation values for the output corresponding to the different types of the sub-regions. The method further includes detecting defects in the sub-regions based on the one scatter plot.

公开(公告)号：US11308606B2

公开(公告)日：2022-04-19

申请号：US16542376

申请日：2019-08-16

Applicant: KLA CORPORATION

Inventor： Junqing Huang ,  Hucheng Lee ,  Sangbong Park ,  Xiaochun Li

IPC: G06K9/00 ,  G06T7/00 ,  H01L27/108 ,  H01L27/11556 ,  G06T7/11 ,  G01N21/95 ,  G01N21/956 ,  H01L27/11582

Abstract: With the disclosed systems and methods for DRAM and 3D NAND inspection, an image of the wafer is received based on the output for an inspection tool. Geometric measurements of a design of a plurality of memory devices on the wafer are received. A care area with higher inspection sensitivity is determined based on the geometric measurements.