PATTERN SEGMENTATION FOR NUISANCE SUPPRESSION

    公开(公告)号:US20240221141A1

    公开(公告)日:2024-07-04

    申请号:US18090447

    申请日:2022-12-28

    CPC classification number: G06T7/0004 G06T7/12 G06T7/136 G06T2207/30148

    Abstract: During semiconductor wafer inspection, an image of a semiconductor wafer is divided into segments. A standard deviation for each of the segments is determined using a difference image. A threshold is then applied to each of the segments. The threshold can be a multiple of the standard deviation. Pixels in the image that include a defect are determined after applying the threshold. The pixels outside the threshold are then labeled as defects-of-interest using the processor.

    Selecting defect detection methods for inspection of a specimen

    公开(公告)号:US11619592B2

    公开(公告)日:2023-04-04

    申请号:US16910011

    申请日:2020-06-23

    Abstract: Methods and systems for selecting defect detection methods for inspection of a specimen are provided. One system includes one or more computer subsystems configured for separating polygons in a care area into initial sub-groups based on a characteristic of the polygons on the specimen and determining a characteristic of noise in output generated by a detector of an inspection subsystem for the polygons in the different initial sub-groups. The computer subsystem(s) are also configured for determining final sub-groups for the polygons by combining any two or more of the different initial sub-groups having substantially the same values of the characteristic of the noise. In addition, the computer subsystem(s) are configured for selecting first and second defect detection methods for application to the output generated by the detector of the inspection subsystem during inspection of the specimen or another specimen.

    Detecting defects in a logic region on a wafer

    公开(公告)号:US10923317B2

    公开(公告)日:2021-02-16

    申请号:US16543596

    申请日:2019-08-18

    Abstract: Methods and systems for detecting defects in a logic region on a wafer are provided. One method includes acquiring information for different types of design-based care areas in a logic region of a wafer. The method also includes designating the different types of the design-based care areas as different types of sub-regions and, for a localized area within the logic region, assigning two or more instances of the sub-regions located in the localized area to a super-region. In addition, the method includes generating one scatter plot for all of the two or more instances of the sub-regions assigned to the super-region. The one scatter plot is generated with different segmentation values for the output corresponding to the different types of the sub-regions. The method further includes detecting defects in the sub-regions based on the one scatter plot.

    ROBUST IMAGE-TO-DESIGN ALIGNMENT FOR DRAM

    公开(公告)号:US20250069354A1

    公开(公告)日:2025-02-27

    申请号:US18480503

    申请日:2023-10-04

    Abstract: Methods and systems for alignment for semiconductor applications are provided. One method includes determining different align-to-design offsets for multiple instances of an alignment target formed on a specimen by separately aligning images of the multiple instances of the alignment target generated by an imaging subsystem to a rendered image for the alignment target with different alignment methods, respectively. The method also includes identifying the multiple instances having a difference between the different align-to-design offsets below a predetermined threshold. In addition, the method includes determining a runtime align-to-design offset for the alignment target from the different align-to-design offsets determined for only the identified multiple instances. That runtime align-to-design offset can then be used in a process performed on the specimen with an imaging subsystem.

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