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公开(公告)号：US10387608B2
公开(公告)日：2019-08-20
申请号：US15727477
申请日：2017-10-06
Applicant: KLA-Tencor Corporation
Inventor： Michael Adel , Tal Shusterman , Chen Dror , Ellis Chang
Abstract: A semiconductor fabrication system includes a target design device and a multi-stage fabrication tool configured to fabricate one or more layers of a sample using the fabrication process. The target design device receives metrology design rules associated with a metrology tool in which the metrology design rules include criteria for one or more physical attributes of metrology targets measurable with the metrology tool. The target design device may further receive process design rules associated with a fabrication process in which the process design rules include criteria for determining process stages of the fabrication process required to fabricate structures with selected physical attributes. The target design device may further generate a target design library including a plurality of metrology targets that satisfy the metrology design rules for the metrology tool and the process design rules for the fabrication process, wherein the target design library includes specifications for fabricating the plurality of metrology targets using two or more process stages of the fabrication process based on the process design rules.
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公开(公告)号：US09910953B2
公开(公告)日：2018-03-06
申请号：US14356551
申请日：2014-03-04
Applicant: KLA-Tencor Corporation
Inventor： Michael Adel , Tal Shusterman , Chen Dror , Ellis Chang
CPC classification number: G06F17/5081 , G03F1/36 , G03F7/70625 , G03F7/70633 , G03F7/70683 , H01L22/12 , H01L22/30
Abstract: A metrology design and verification framework is provided, which includes methods and systems for metrology structure identification in an integrated circuit design data block, design rule checking, hierarchal design of metrology target structures to minimize random errors, and metrology design rule verification of metrology target design files. In-die metrology targets are identified using various filtering methods and/or designed as hierarchical structure within dies or outside the dies. Particularly, metrology target design files are generated, which are hierarchical in structure and compatible with design rule checks. Design rule check takes into account the hierarchical and often repetitive target designs in the verification process. Layouts may be verified using design rule checks at different levels of design rules, which may be combined to remove rule violations and errors prior to actual target production.
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公开(公告)号：US20180032662A1
公开(公告)日：2018-02-01
申请号：US15727477
申请日：2017-10-06
Applicant: KLA-Tencor Corporation
Inventor： Michael Adel , Tal Shusterman , Chen Dror , Ellis Chang
CPC classification number: G06F17/5081 , G03F1/36 , G03F7/70625 , G03F7/70633 , G03F7/70683 , H01L22/12 , H01L22/30
Abstract: A semiconductor fabrication system includes a target design device and a multi-stage fabrication tool configured to fabricate one or more layers of a sample using the fabrication process. The target design device receives metrology design rules associated with a metrology tool in which the metrology design rules include criteria for one or more physical attributes of metrology targets measurable with the metrology tool. The target design device may further receive process design rules associated with a fabrication process in which the process design rules include criteria for determining process stages of the fabrication process required to fabricate structures with selected physical attributes. The target design device may further generate a target design library including a plurality of metrology targets that satisfy the metrology design rules for the metrology tool and the process design rules for the fabrication process, wherein the target design library includes specifications for fabricating the plurality of metrology targets using two or more process stages of the fabrication process based on the process design rules.
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