公开(公告)号：US10303839B2

公开(公告)日：2019-05-28

申请号：US15385564

申请日：2016-12-20

Applicant: KLA-Tencor Corporation

Inventor： Sagar A. Kekare

IPC: G06F17/50

Abstract: Methods and systems for determining electrically relevant placement of metrology targets using design analysis are disclosed. The method may include: identifying at least one critical design element of an integrated circuit based on a design of the integrated circuit; determining whether the design of the integrated circuit allows for an insertion of a metrology target in a vicinity of the at least one critical design element; and modifying the design of the integrated circuit by inserting a metrology target into the vicinity of the at least one critical design element when the design of the integrated circuit allows for the insertion of the metrology target.

公开(公告)号：US20170351804A1

公开(公告)日：2017-12-07

申请号：US15385564

申请日：2016-12-20

Applicant: KLA-Tencor Corporation

Inventor： Sagar A. Kekare

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072

Abstract: Methods and systems for determining electrically relevant placement of metrology targets using design analysis are disclosed. The method may include: identifying at least one critical design element of an integrated circuit based on a design of the integrated circuit; determining whether the design of the integrated circuit allows for an insertion of a metrology target in a vicinity of the at least one critical design element; and modifying the design of the integrated circuit by inserting a metrology target into the vicinity of the at least one critical design element when the design of the integrated circuit allows for the insertion of the metrology target.

公开(公告)号：US20150363537A1

公开(公告)日：2015-12-17

申请号：US14735596

申请日：2015-06-10

Applicant: KLA-Tencor Corporation

Inventor： Sagar A. Kekare ,  Sergei G. Bakarian

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5009 ,  H01L22/12 ,  H01L22/20

Abstract: Methods and systems for extracting comprehensive design guidance for in-line process control of wafers are provided. One method includes automatically identifying potential marginalities in a design for a device to be formed on a wafer. The method also includes automatically generating information for the potential marginalities. The automatically generated information is used to set up process control for the wafer.

Abstract translation: 提供了用于提取晶圆在线过程控制的综合设计指导的方法和系统。 一种方法包括自动识别要在晶片上形成的器件的设计中的潜在边缘。 该方法还包括为潜在的边际自动生成信息。 自动生成的信息用于设置晶圆的过程控制。

公开(公告)号：US20150039954A1

公开(公告)日：2015-02-05

申请号：US14450027

申请日：2014-08-01

Applicant: KLA-Tencor Corporation

Inventor： Sagar A. Kekare

IPC: G01R31/3185

CPC classification number: G01R31/318511 ,  H01L22/14 ,  H01L22/20

Abstract: Methods and systems for determining one or more parameters for electrical testing of a wafer are provided. One method includes determining electrical test paths through a device being formed on a wafer and physical layout components in different layers of the device corresponding to each of the electrical test paths. The method also includes determining one or more parameters of electrical testing for the wafer based on one or more characteristics of the electrical test paths. In addition, the method includes acquiring information for one or more characteristics of a physical version of the wafer. The information is generated by performing an inline process on the physical version of the wafer. The method further includes altering at least one of the one or more parameters of the electrical testing for the wafer based on the acquired information.

Abstract translation: 提供了用于确定晶片电测试的一个或多个参数的方法和系统。 一种方法包括确定通过在晶片上形成的器件的电测试路径以及对应于每个电测试路径的器件的不同层中的物理布局组件。 该方法还包括基于电测试路径的一个或多个特性确定晶片的电测试的一个或多个参数。 此外，该方法包括获取关于晶片的物理版本的一个或多个特性的信息。 通过在晶片的物理版本上执行在线处理来生成信息。 该方法还包括基于所获取的信息来改变晶片的电测试的一个或多个参数中的至少一个。

公开(公告)号：US09400865B2

公开(公告)日：2016-07-26

申请号：US14735596

申请日：2015-06-10

Applicant: KLA-Tencor Corporation

Inventor： Sagar A. Kekare ,  Sergei G. Bakarian

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5009 ,  H01L22/12 ,  H01L22/20

Abstract: Methods and systems for extracting comprehensive design guidance for in-line process control of wafers are provided. One method includes automatically identifying potential marginalities in a design for a device to be formed on a wafer. The method also includes automatically generating information for the potential marginalities. The automatically generated information is used to set up process control for the wafer.

Abstract translation: 提供了提供晶圆在线过程控制综合设计指导的方法和系统。 一种方法包括自动识别要在晶片上形成的器件的设计中的潜在边缘。 该方法还包括为潜在的边际自动生成信息。 自动生成的信息用于设置晶圆的过程控制。

公开(公告)号：US09689923B2

公开(公告)日：2017-06-27

申请号：US14450027

申请日：2014-08-01

Applicant: KLA-Tencor Corporation

Inventor： Sagar A. Kekare

IPC: G06F17/50 ,  G01R31/3185 ,  H01L21/66

CPC classification number: G01R31/318511 ,  H01L22/14 ,  H01L22/20

Abstract: A method and a system for determining one or more parameters for electrical testing of a wafer are provided. One method includes determining electrical test paths through a device being formed on a wafer and physical layout components in different layers of the device corresponding to each of the electrical test paths. The method also includes determining one or more parameters of electrical testing for the wafer based on one or more characteristics of the electrical test paths. In addition, the method includes acquiring information for one or more characteristics of a physical version of the wafer. The information is generated by performing an inline process on the physical version of the wafer. The method further includes altering at least one of the one or more parameters of the electrical testing for the wafer based on the acquired information.